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參數(shù)資料
| 型號(hào)： | 75P52100 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | NETWORK SEARCH ENGINE 64K x 72 Entries |
| 中文描述： | 網(wǎng)絡(luò)搜索引擎64K的× 72項(xiàng) |
| 文件頁(yè)數(shù)： | 3/3頁(yè) |
| 文件大?。?/td> | 443K |
| 代理商： | 75P52100 |
6.42
Network Search Engine 64K x 72 Entries Datasheet Brief 75P52100
Signal Descriptions
Pin Function
I/O
Description
NSE Request Bus:
Request Strobe
Input
This input signifies a valid input request and signals the start of an NSE operation cycle.
Command
Bus
Instruction
Input
These two fields of the Command bus define the instruction to be performed by the NSE and the lookup
type. The lookup type is selected only for operational type commands (Lookups, Learns) and is a "dont
care" for maintenance type commands (all Reads and Writes).
Lookup Type
Input
Global Mask
Register Select
Input
This field is wthin the Command bus. During Lookup or Write operations, this field defines which of the
Global Mask Register groups are being accessed. This field is a "don't care" for Read, SRAM No Wait
Read, and Learn Operations.
Comparand and
Result Register
Select
Input
This is a multiplexed field within the Command Bus that specifies both the Result Register to store the
Index into, and the Comparand Register to use. This field is sampled every input clock cycle. The first
cycle decodes the selected Comparand Register and the second decodes the selected Result Register
Request Data Bus
Input/Output
Three State
The Request Data Bus is a multiplexed address/data bus used to performreads (and writes) from(to) the
NSE, and to present search data for lookups.
NSE Response Bus:
Index Bus
Address
Output
Three State
This bus is used to drive the address of an external SRAM, or feedback Lookup result information
directly to the NSE's ASIC/FPGA. The Index Bus contain the encoded location at which the compare was
found, the address of the NSE which found the result and the Lookup type.
Device ID
Lookup Type
Chip Enable/ Output Enable
Output
Three State
This signal is driven along wth the Index Bus. It is connected to the
CE
input pin of a ZBT SRAMor to the
OE
pin of a PBSRAM
Write Enable
Output
Three State
This signal is driven along wth the Index bus. It is used to assert the
WE
pin of an external SRAM. It is
active for both SRAMwrite operations and the Learn command.
Read Acknowledge
Output
This signal is sent back when the data is read fromthe NSE on the Request Data Bus, or when the data
being read fromthe associated external SRAM.
Match Acknowedge
Output
This is signal is sent with the Index. It wll be driven lowif there was no match, high if a match was found.
Valid
Lookup Bit
Output
This signal is sent wth the Index. It wll be driven high upon the completion of a lookup, even if the
lookup did not result in a hit.
Multi Match
Output
Output
(Open Drain)
This signal is sent wth the Index. It shall go active when a) multiple hits occur in one segment; or b) one
or more hits occur in two (or more) segments; or c) one or more hits occur in multiple devices that are
depth cascaded.
Depth Expansion:
Device Address
Input
These three DC pins are used to define the Device Address for each of the eight possible depth
expanded NSE devices in an NSE system
Match
Input
Input
The Match Input signal is driven by all upstreamMatch Output signals. This indicates to all down stream
NSEs that a hit in a higher priority NSE has occurred.
Match
Output
Output
The Match Output signal signifies that a match has occurred in the NSE. The signal is fed into a Match
Input line of all lower priority NSE(s).
Clock and Initialization:
Clock Input
Input
All inputs and outputs are referenced to the positive edge of this clock.
Clock Phase Enable
Input
This signal is used to generate an internal clock at the frequency of the input clock.
Reset
Input
This pin wll force all outputs to a high impedence condition, as well as clearing the NSE enable bit.
Advance Burst Address
Input
This signal wll advance an internal address counter to allowfor burst writes when writing to the Data/Mask
memory in the NSE. This provides a mechanismto conveniently initialize the NSE memory.
Last NSE
Input
This pin defines which NSE device wll drive the ASIC Feedback signals to the ASIC/FPGA.
Last SRAM
Input
This pin defines which NSE device wll drive the SRAM control signals
CE
/
OE
and
WE
. It also defaults
this device to driving the Index Bus when there is no ongoing operation preventing the bus fromfloating.
5333 tbl 01
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 75P52100S100BX | 制造商:Integrated Device Technology Inc 功能描述:64K ENTRY FULL TERN |
| 75P52100S100RX | 制造商:Integrated Device Technology Inc 功能描述:TCAM 4.5MB NETWORK SEARCH ENGINE |
| 75PA-024 | 制造商:JFW 制造商全稱(chēng):JFW Industries, Inc. 功能描述:PROGRAMMABLE ATTENUATOR ASSEMBLY |
| 75PA-050 | 制造商:JFW 制造商全稱(chēng):JFW Industries, Inc. 功能描述:PROGRAMMABLE ATTENUATOR ASSEMBLY |
| 75PAR/CAP/SPL/FL30 130V | 制造商:OSRAM 功能描述:75PAR38/HAL/FL30 130V 15/CS 1/SKU |
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