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參數(shù)資料
| 型號(hào)： | 75P42100 |
| 廠(chǎng)商： | Integrated Device Technology, Inc. |
| 英文描述： | NETWORK SEARCH ENGINE 32K x 72 Entries |
| 中文描述： | 網(wǎng)絡(luò)搜索引擎32K的× 72項(xiàng) |
| 文件頁(yè)數(shù)： | 2/3頁(yè) |
| 文件大?。?/td> | 67K |
| 代理商： | 75P42100 |
2
Network Search Engine 32K x 72 Entries Datasheet Brief 75P42100
SRAMInterface
The NSE provides all required address and control signals for a
glueless SRAMinterface. The NSE provides a pipelined bypass path for
reads or writes to the external SRAM. The ASIC/FPGA handles the
pipelining of the data to and fromthe SRAM.
Registers
There are four basic types of registers supported:
I
Configuration Registers are used at initialization to define the
segmentation of the entries, timng of outputs and the SRAMinterface.
I
Global Mask Registers are provided to support Lookup
instructions by masking individual bits during a search.
I
Comparand Registers assist in the Learn Instruction.
I
Result Registers are used to store the resulting index of a
search froma Lookup or Learn operation.
Synchronous Burst Write
The burst write feature has no limt on the number of continuous write
accesses and supports initialization of the NSE.
Width Segmentation Capability
The NSEs are capable of performng lookups for comparisons on data
structures of 72 bits, 144 bits, 288 bits and 576 bits. These devices has
can be configured to meet various systemrequirements.
I
Single Width Array
I
Multiple Width Arrays within a Single Device
Multi Match
The Multi-Match feature signals to the user that more than one match
has resulted. The result of the lookup, which defines the highest priority
match, is sent along with the Multi-Match signal.
Power Savings and Classification Features
See the full IDT75P42100 Datasheet for more information.
Functional Highlights
Figure 1.1
Bus Interface
The NSE utilizes a dual bus interface consisting of the NSE Request
Bus and the NSE Response Bus.
The NSE Request Bus is comprised of the Command Bus and the
Request Data Bus. The Command Bus handles the instruction to the NSE
while the Request Data Bus is the main data path to the NSE.
The 72 bit bi-directional Request Data Bus functions as a multiplexed
address and data bus, which performs the writing and reading of NSE
entries, as well as presenting lookup data to the device.
The NSE Response Bus is comprised of an independent unidirec-
tional Index Bus which drives the result of the lookup (or index) to either
an SRAMdevice or an ASIC. In addition to driving the Index, the NSE
Response Bus also drives the associated SRAMcontrol signals (
CE
/
OE
,
and
WE
) for either ZBT or Synchronous Pipeline Burst SRAMdevices.
Command Bus
The Command Bus loads the specific instructions into the NSE. These
include:
I
Read or Write
A Read or Write instruction operates on a specified data entry, mask
entry, or register.
Data and Mask Array
The NSE has Data cell entries and associ-
ated Mask cell entries as shown in Fig. 1.1. This
combination of Data and Mask cell entries en-
ables the NSE to store 0, 1 or X, making it a full
ternary Network Search Engine. During a
lookup operation, both arrays are used along
with a Global Mask Register to find a match to a
requested data word.
A5346 drw 03
Data
Mask
I
SRAMNo Wait Read
An SRAMNo Wait Read is a Read instruction to an external SRAMthat
can be pipelined within a series of operations and does not require the user
to wait for the Read to complete before loading the next instruction.
I
Dual Write
In addition to individual writes, the NSE has the ability to perform
simultaneous writes to a Data entry and a respective external SRAM
location.
I
Lookup
A lookup can be requested in 72-bit, 144-bit, 288-bit or 576-bit widths.
A 36-bit lookup can be accomplished by using two Global Mask Registers.
I
Learn
The NSE implements a fully autonomous Learn Instruction, which
provides a mechanismfor the user to write a lookup entry into an unused
location in the NSE and the associated data in external SRAM This allows
the user to update an entry into the NSE which had not previously been
stored. The Learn writes the new entry, making it available for future
lookups.
Features
I
Full Ternary 32K x 72 bit content addressable memory
I
Upgradeable to 64K x 72 and 128K x 72 NSEs
I
Power Management
I
Global Mask Registers
I
Segments individually configurable
I
36/72/144/288/576 multiple width lookups
I
100Msustained lookups per second at 72 and 144 width lookups
I
Burst write for high speed table updates
I
Multi-match
I
Learn new entries
I
Dual bus interface
I
Cascadable to 8 devices with no glue logic or latency penalty
I
Glueless interface to standard ZBT or
Synchronous Pipelined Burst SRAMs
I
Boundary Scan JTAG Interface (IEEE 1149.1compliant)
I
1.8V core power supply
I
2.5V V
BIAS
power supply
I
User selectable 2.5V or 1.8V I/O supply
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 75P52100 | NETWORK SEARCH ENGINE 64K x 72 Entries |
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| 75T2089 | DTMF Transceivers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 75P42100_0509 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:NETWORK SEARCH ENGINE 32K x 72 Entries |
| 75P42100S100BX | 制造商:Integrated Device Technology Inc 功能描述:2MB (32KX72) ENTRY FULL TERNARY IP CO-PR |
| 75P42100S83BX | 制造商:Integrated Device Technology Inc 功能描述:2MB HIGH PERFORMANCE NSE |
| 75P52100 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:NETWORK SEARCH ENGINE 64K x 72 Entries |
| 75P52100S100BX | 制造商:Integrated Device Technology Inc 功能描述:64K ENTRY FULL TERN |
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