參數(shù)資料
型號(hào): 75N43102
廠商: Integrated Device Technology, Inc.
英文描述: NETWORK SEARCH ENGINE 32K x 72 Entries
中文描述: 網(wǎng)絡(luò)搜索引擎32K的× 72項(xiàng)
文件頁(yè)數(shù): 2/4頁(yè)
文件大?。?/td> 42K
代理商: 75N43102
2
Network Search Engine 32K x 72 Entries Datasheet Brief 75N43102
Registers
There are three basic types of registers supported:
I
Configuration Registers are used at initialization to define the
segmentation of the entries.
I
Global Mask Registers are provided to support Lookup
instructions by masking individual bits during a search.
I
Reply Width Registers are used with Lookup operations.
Functional Highlights
Figure 1.1
Bus Interface
The NSE utilizes a dual bus interface consisting of the NSE Request
Bus and the NSE Response Bus.
The NSE Request Bus is comprised of the Command Bus and the
Request Data Bus. The Command Bus handles the instruction to the NSE
while the Request Data Bus is the main data path to the NSE.
The 72 bit bi-directional Request Data Bus functions as a multiplexed
address and data bus, which performs the writing and reading of NSE
entries, as well as presenting lookup data to the device.
The NSE Response Bus is comprised of an independent unidirec-
tional Index Bus which drives the result of the lookup (or index) to an ASIC.
Data and Mask Array
The NSE has Data cell entries and associ-
ated Mask cell entries as shown in Fig. 1.1. This
combination of Data and Mask cell entries en-
ables the NSE to store 0, 1 or X, making it a full
ternary Network Search Engine. During a
lookup operation, both arrays are used along
with a Global Mask Register to find a match to a
requested data word.
A6435 drw 03
Data
Mask
Command Bus
The Command Bus loads the specific instructions into the NSE. These
include:
I
Read or Write
A Read or Write instruction operates on a specified data entry, mask
entry, or register.
I
Lookup
A lookup can be requested in 72-bit, 144-bit or 288-bit widths. A 36-
bit lookup can be accomplished by using two Global Mask Registers.
Features
I
Full Ternary 32K x 72 bit content addressable memory
I
Global Mask Registers
I
72/144/288 multiple width lookups
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62.5Msustained lookups per second at 72 and 144 width lookups
I
Dual bus interface
I
Cascadable to 2 devices with no glue logic or latency penalty
I
Boundary Scan JTAG Interface (IEEE 1149.1compliant)
I
1.5V match power supply
I
2.5V core and I/O power supply
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