- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382825 > 75N42102 (Integrated Device Technology, Inc.) NETWORK SEARCH ENGINE 32K x 72 Entries PDF資料下載
參數(shù)資料
| 型號(hào)： | 75N42102 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | NETWORK SEARCH ENGINE 32K x 72 Entries |
| 中文描述： | 網(wǎng)絡(luò)搜索引擎32K的× 72項(xiàng) |
| 文件頁數(shù)： | 3/3頁 |
| 文件大?。?/td> | 437K |
| 代理商： | 75N42102 |
6.42
Network Search Engine 32K x 72 Entries Datasheet Brief 75N42102
Signal Descriptions
Pin Function
I/O
Description
NSE Request Bus:
Request Strobe
Input
This input signifies a valid input request and signals the start of an NSE operation cycle.
Command Bus
Input
Defines the instruction to be performed by the NSE and selects Global Mask registers and Search Result
registers.
Request Data Bus
Input/Output
Three State
The Request Data Bus is a multiplexed address/data bus used to performreads (and writes) from(to) the
NSE, and to present search data for lookups.
NSE Response Bus:
Index Bus
Output
Three State
This bus is used to drive the address of an external SRAM, or feedback Lookup result information
directly to the NSE's ASIC/FPGA. The Index Bus contains the encoded location at which the compare
was found.
Chip Enable/ Output Enable
Output
Three State
This signal is driven along wth the Index Bus. It is connected to the
CE
input pin of a ZBT SRAMor to the
OE
pin of a PBSRAM
Write Enable
Output
Three State
This signal is driven along wth the Index bus. It is used to assert the
WE
pin of an external SRAM. It is
active for SRAMwrite operations.
Read Acknowledge
Output
This signal is sent back when the data is read fromthe NSE on the Request Data Bus, or when the data
being read fromthe associated external SRAM.
Match Acknowedge
Output
This is signal is sent with the Index. It wll be driven lowif there was no match, high if a match was found.
Valid
Lookup Bit
Output
This signal is sent wth the Index. It wll be driven high upon the completion of a lookup, even if the
lookup did not result in a hit.
Clock and Initialization:
Clock Input
Input
All inputs and outputs are referenced to the positive edge of this clock.
Clock Phase Enable
Input
This signal is used to generate an internal clock at the frequency of the input clock.
Reset
Input
This pin wll force all outputs to a high impedence condition, as well as clearing the NSE enable bit.
Depth Expansion:
Configuration In
Input
Configures the Device ID at power up.
Configuration Out
Output
Configures the Device ID at power up.
Match
Input
Input
The Match Input signal is driven by all upstreamMatch Output signals. This indicates to all down stream
NSEs that a hit in a higher priority NSE has occurred.
Match
Output
Output
The Match Output signal signifies that a match has occurred in the NSE. The signal is fed into a Match
Input line of all lower priority NSE(s).
6457 tbl 01
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 75N43102 | NETWORK SEARCH ENGINE 32K x 72 Entries |
| 75P42100 | NETWORK SEARCH ENGINE 32K x 72 Entries |
| 75P52100 | NETWORK SEARCH ENGINE 64K x 72 Entries |
| 75T2089-IP | TV 22C 22#22D PIN RECP |
| 75T2089 | DTMF Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 75N43102 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:NETWORK SEARCH ENGINE 32K x 72 Entries |
| 75N43102_05 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:NETWORK SEARCH ENGINE 32K x 72 Entries |
| 75N43102S62BC | 制造商:Integrated Device Technology Inc 功能描述:2MB LOW COST HIGH PERFORMANCE NSE |
| 75N4R12 | 制造商: 功能描述: |
| 75N75 | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:75Amps, 75Volts N-CHANNEL POWER MOSTFET |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。