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參數(shù)資料
| 型號： | 74VHCT573ATTR |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 通用總線功能 |
| 英文描述： | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING |
| 中文描述： | 八路D型，3態(tài)輸出的非反相鎖存 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 74K |
| 代理商： | 74VHCT573ATTR |
74VHCT573A
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
February 2000
I
HIGHSPEED:t
PD
=5.4ns(TYP.)atV
CC
= 5V
I
LOWPOWERDISSIPATION:
I
CC
=4
μ
A(MAX.) at T
A
=25
o
C
I
COMPATIBLEWITH TTL OUTPUTS:
V
IH
=2V (MIN),V
IL
= 0.8V(MAX)
I
POWERDOWN PROTECTIONON INPUTS&
OUTPUTS
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 8 mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 4.5Vto 5.5V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES573
I
IMPROVEDLATCH-UP IMMUNITY
I
LOWNOISE:V
OLP
= 0.9V(Max.)
DESCRIPTION
The 74VHCT573A is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT
NON
INVERTING
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
(OE).
fabricated
with
While the LE input is held at a high level, the Q
outputswill follow the data inputs precisely.
When the LE is taken low, the Q outputs will be
latchedpreciselyat thelogic level of D input data.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedancestate.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface5V to 3V.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
equipped with
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
TSSOP
ORDER CODES
TUBE
74VHCT573AM
PACKAGE
SOP
TSSOP
T & R
74VHCT573AMTR
74VHCT573ATTR
1/10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74VHCT573AM | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING |
| 74VHCT573AMTR | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING |
| 74VHCT573 | Octal D-Type Latch with 3-STATE Outputs |
| 74VHCT573A | Octal D-Type Latch with 3-STATE Outputs |
| 74VHCT573AM | Octal Transparent D-Type Latches With 3-State Outputs 20-PDIP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74VHCT574 | 制造商:NAT 功能描述: 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74VHCT574AFT | 功能描述:IC D-TYPE POS TRG SNGL 20TSSOP 制造商:toshiba semiconductor and storage 系列:74VHCT 包裝:剪切帶（CT） 零件狀態(tài):在售 功能:標(biāo)準(zhǔn) 類型:D 型 輸出類型:三態(tài)，非反相 元件數(shù):1 每元件位數(shù):8 時鐘頻率:140MHz 不同 V，最大 CL 時的最大傳播延遲:10.4ns @ 5V，50pF 觸發(fā)器類型:正邊沿 電流 - 輸出高，低:8mA，8mA 電壓 - 電源:4.5 V ~ 5.5 V 電流 - 靜態(tài)（Iq):4μA 輸入電容:4pF 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 基本零件編號:74VHCT574 標(biāo)準(zhǔn)包裝:1 |
| 74VHCT574AFT(BE) | 制造商:Toshiba America Electronic Components 功能描述:IC D-TYPE POS TRG SNGL 20TSSOP |
| 74VHCT574AM | 功能描述:觸發(fā)器 Oct D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74VHCT574AM_Q | 功能描述:觸發(fā)器 Oct D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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