參數(shù)資料
型號(hào): 74VHCT245AT
廠商: 意法半導(dǎo)體
英文描述: OCTAL BUS TRANSCEIVER 3-STATE
中文描述: 八路總線收發(fā)器三態(tài)
文件頁數(shù): 1/9頁
文件大?。?/td> 68K
代理商: 74VHCT245AT
74VHCT245A
OCTAL BUS
TRANSCEIVER (3-STATE)
PRELIMINARY DATA
August 1999
ORDER CODES :
74VHCT245AM
74VHCT245AT
M
(Micro Package)
I
HIGHSPEED:t
PD
=4.5ns(TYP.)atV
CC
= 5V
I
LOWPOWERDISSIPATION:
I
CC
=4
μ
A(MAX.) at T
A
=25
o
C
I
COMPATIBLEWITH TTL OUTPUTS:
V
IH
=2V (MIN),V
IL
= 0.8V(MAX)
I
POWERDOWN PROTECTIONON INPUTS&
OUTPUTS
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 8 mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 4.5Vto 5.5V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES245
I
IMPROVEDLATCH-UP IMMUNITY
I
LOWNOISE:V
OLP
= 0.9V(Max.)
DESCRIPTION
The 74VHCT245A is an advanced high-speed
CMOS OCTAL BUS TRANSCEIVER (3-STATE)
fabricated with sub-micron silicon gate
double-layermetal wiring C
2
MOS technology.
This IC is intended for two-way asynchronous
communication
between
direction of data trasmission is determined by the
and
data
busses;
the
T
(TSSOPPackage)
level of the DIR input. The enable input G can be
used to disable the device so that the busses are
effectivelyisolated.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
IT IS PROHIBITED TO APPLY A SIGNAL TO A
TERMINAL WHEN IT IS IN OUTPUT MODE
AND WHEN A BUS TERMINAL IS FLOATING
(HIGH IMPEDANCE STATE) IT IS REQUESTED
TO FIX THE INPUT LEVEL BY MEANS OF
EXTERNAL
PULL
DOWN
RESISTOR.
equipped with
OR
PULL
UP
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/9
相關(guān)PDF資料
PDF描述
74VHCT245A Octal Buffer/Line Driver with 3-STATE Outputs
74VHCT245AM Octal Buffer/Line Driver with 3-STATE Outputs
74VHCT245AMTC Octal D-Type Flip-Flops With Clear 20-PDIP -40 to 85
74VHCT245AN Octal Buffer/Line Driver with 3-STATE Outputs
74VHCT245ASJ Octal Buffer/Line Driver with 3-STATE Outputs
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