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  • 參數(shù)資料
    型號(hào): 74VHCT244AM
    廠商: Fairchild Semiconductor
    文件頁(yè)數(shù): 5/9頁(yè)
    文件大小: 0K
    描述: IC BUFF/DVR TRI-ST DUAL 20SOIC
    標(biāo)準(zhǔn)包裝: 36
    系列: 74VHCT
    邏輯類型: 緩沖器/線路驅(qū)動(dòng)器,非反相
    元件數(shù): 2
    每個(gè)元件的位元數(shù): 4
    輸出電流高,低: 8mA,8mA
    電源電壓: 4.5 V ~ 5.5 V
    工作溫度: -40°C ~ 85°C
    安裝類型: 表面貼裝
    封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
    供應(yīng)商設(shè)備封裝: 20-SOIC
    包裝: 管件
    74VHCT244A
    Octal
    Buff
    er/Line
    Driver
    with
    3-ST
    A
    TE
    Outputs
    1997 Fairchild Semiconductor Corporation
    www.fairchildsemi.com
    74VHCT244A Rev. 1.3
    5
    AC Electrical Characteristics
    Notes:
    7. Parameter guaranteed by design. tOSLH = |tPLH max – tPLH min|; tOSHL = |tPHL max – tPHL min|
    8. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
    current consumption without load. Average operating current can be obtained by the equation:
    ICC (Opr.) = CPD VCC fIN + ICC / 8 (per F/F). The total CPD when n pcs. of the Octal D Flip-Flop operates
    can be calculated by the equation: CPD (total) = 20 + 12n
    Symbol
    Parameter
    VCC (V)
    Conditions
    TA = 25°C
    TA = –40°C
    to +85°C
    Units
    Min.
    Typ. Max. Min.
    Max.
    tPLH, tPHL
    Propagation Delay
    Time
    5.0 ± 0.5
    CL = 15pF
    5.4
    7.4
    1.0
    8.5
    ns
    CL = 50pF
    5.9
    8.4
    1.0
    9.5
    tPZL, tPZH
    3-STATE Output
    Enable Time
    5.0 ± 0.5 RL = 1k CL = 15pF
    7.7
    10.4
    1.0
    12.5
    ns
    CL = 50pF
    8.2
    11.4
    1.0
    13.5
    tPLZ, tPHZ
    3-STATE Output
    Disable Time
    5.0 ± 0.5 RL = 1k CL = 50pF
    8.8
    11.4
    1.0
    13.0
    ns
    tOSLH, tOSHL Output to Output
    Skew
    5.0 ± 0.5 (7)
    1.0
    ns
    CIN
    Input Capacitance
    VCC = Open
    4
    10
    pF
    COUT
    Output Capacitance
    VCC = 5.0V
    9
    pF
    CPD
    Power Dissipation
    Capacitance
    (8)
    18
    pF
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