參數(shù)資料
型號(hào): 74VHCT16373ATTR
廠商: 意法半導(dǎo)體
英文描述: 16-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTING
中文描述: 16位D型鎖存器三態(tài)輸出的非反相
文件頁數(shù): 1/10頁
文件大?。?/td> 263K
代理商: 74VHCT16373ATTR
1/10
February 2003
I
HIGH SPEED:
t
PD
= 5.0 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
μ
A (MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
=2V (MIN.) V
IL
= 0.8 (MAX.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.9V (MAX.)
I
I
I
I
I
I
I
I
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DESCRIPTION
The 74VHCT16373A is an advanced high-speed
CMOS 16 BIT D-TYPE LATCH with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(nOE).
While the nLE input is held at a high level, the nQ
outputs will follow the data (D) inputs.
When the nLE is taken LOW, the nQ outputs will
be latched at the logic level of D data inputs.
When the (nOE) input is low, the nQ outputs will
be in a normal logic state (high or low logic level);
when nOE is at high level ,the outputs will be in a
high impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
74VHCT16373A
16-BIT D-TYPE LATCH
WITH 3-STATE OUTPUTS NON INVERTING
ORDER CODES
PACKAGE
TUBE
T & R
TSSOP
74VHCT16373ATTR
TSSOP
PIN CONNECTION
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