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參數(shù)資料
| 型號： | 74VHC573MTR |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 通用總線功能 |
| 英文描述： | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING |
| 中文描述： | 八路D型，3態(tài)輸出的非反相鎖存 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 289K |
| 代理商： | 74VHC573MTR |
1/14
November 2004
I
HIGH SPEED: t
PD
= 5.0 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
μ
A (MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.9V (MAX.)
I
I
I
I
I
I
I
I
I
DESCRIPTION
The 74VHC573 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while (OE) is in high level, the outputs will be in a
high impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
TSSOP
74VHC573MTR
74VHC573TTR
TSSOP
SOP
Rev. 5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74VHC573TTR | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING |
| 74VHC573MTC | Octal D-Type Latch with 3-STATE Outputs |
| 74VHC573 | Octal D-Type Latch with 3-STATE Outputs |
| 74VHC573M | Hex Schmitt-Trigger Inverters 14-SSOP -40 to 85 |
| 74VHC573N | Hex Schmitt-Trigger Inverters 14-SOIC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74VHC573MTX | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74VHC573MX | 功能描述:閉鎖 Octal D-Type Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74VHC573N | 功能描述:閉鎖 Octal D-Type Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74VHC573N | 制造商:Fairchild Semiconductor Corporation 功能描述:74VHC CMOS 74VHC573 DIP20 5.5V |
| 74VHC573N_Q | 功能描述:閉鎖 Octal D-Type Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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