參數(shù)資料
型號: 74VHC573M
廠商: Fairchild Semiconductor
文件頁數(shù): 5/9頁
文件大小: 0K
描述: IC LATCH OCT D-TYPE 3ST 20-SOIC
標準包裝: 36
系列: 74VHC
邏輯類型: D 型透明鎖存器
電路: 8:8
輸出類型: 三態(tài)
電源電壓: 2 V ~ 5.5 V
獨立電路: 1
延遲時間 - 傳輸: 4.5ns
輸出電流高,低: 8mA,8mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 20-SOIC
包裝: 管件
產(chǎn)品目錄頁面: 1213 (CN2011-ZH PDF)
74VHC573
Octal
D-T
ype
Latc
h
with
3-ST
A
TE
Outputs
1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC573 Rev. 1.3
5
AC Electrical Characteristics
Notes:
3. Parameter guaranteed by design. tOSLH = |tPLH max – tPLH min|; tOSHL = |tPHL max – tPHL min|
4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
ICC (Opr.) = CPD VCC fIN + ICC / 8 (per Latch). The total CPD when n pcs. of the Latch operates can be
calculated by the equation: CPD(total) = 21 + 8n.
AC Operating Requirements
Symbol
Parameter
VCC (V)
Conditions
TA = 25°C
TA = –40°C
to +85°C
Units
Min.
Typ.
Max.
Min.
Max.
tPLH, tPHL
Propagation Delay
Time (LE to On)
3.3 ± 0.3
CL = 15pF
7.6
11.9
1.0
14.0
ns
CL = 50pF
10.1
15.4
1.0
17.5
5.0 ± 0.5
CL = 15pF
5.0
7.7
1.0
9.0
CL = 50pF
6.5
9.7
1.0
11.0
tPLH, tPHL
Propagation Delay
Time (D–On)
3.3 ± 0.3
CL = 15pF
7.0
11.0
1.0
13.0
ns
CL = 50pF
9.5
14.5
1.0
16.5
5.0 ± 0.5
CL = 15pF
4.5
6.8
1.0
8.0
CL = 50pF
6.0
8.8
1.0
10.0
tPZL, tPZH
3-STATE Output
Enable Time
3.3 ± 0.3
RL = 1k CL = 15pF
7.3
11.5
1.0
13.5
ns
CL = 50pF
9.8
15.0
1.0
17.0
5.0 ± 0.5
CL = 15pF
5.2
7.7
1.0
9.0
CL = 50pF
6.7
9.7
1.0
11.0
tPLZ, tPHZ
3-STATE Output
Disable Time
3.3 ± 0.3
RL = 1k CL = 50pF
10.7
14.5
1.0
16.5
ns
5.0 ± 0.5
CL = 50pF
6.7
9.7
1.0
11.0
tOSLH, tOSHL Output to Output
Skew
3.3 ± 0.3
(3)
CL = 50pF
1.5
ns
5.0 ± 0.5
CL = 50pF
1.0
CIN
Input Capacitance
VCC = Open
4
10
pF
COUT
Output Capacitance
VCC = 5.0V
6
pF
CPD
Power Dissipation
Capacitance
(4)
29
pF
Symbol
Parameter
VCC
(V)
TA = 25°C
TA = –40°C to
+85°C
Units
Min.
Typ.
Max.
Min.
Max.
tw(H), tw(L) Minimum Pulse Width (LE)
3.3 ± 0.3
5.0
ns
5.0 ± 0.5
5.0
tS
Minimum Setup Time
3.3 ± 0.3
3.5
ns
5.0 ± 0.5
3.5
tH
Minimum Hold Time
3.3 ± 0.3
1.5
ns
5.0 ± 0.5
1.5
相關PDF資料
PDF描述
74VHC373M IC LATCH OCTAL D-TYPE 20-SOIC
1546212-8 TERM BLOCK HEADER 8POS VERT 5MM
1546210-8 TERM BLOCK HEADER 8POS R/A 5MM
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