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參數(shù)資料
| 型號： | 74VHC4040MTCX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COUNTER VIN 12STAGE 16TSSOP |
| 標準包裝： | 1 |
| 系列： | 74VHC |
| 邏輯類型： | 二進制計數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 12 |
| 復位： | 異步 |
| 計數(shù)速率： | 210MHz |
| 觸發(fā)器類型： | 負邊沿 |
| 電源電壓： | 2 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | 74VHC4040MTCXDKR |
74VHC4040
12-Sta
g
e
Binar
y
Counter
1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC4040 Rev. 1.3
6
AC Electrical Characteristics
Note:
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
ICC (Opr.) = CPD VCC fN + ICC
AC Operating Requirements
Symbol
Parameter
VCC (V)
Conditions
TA = +25°C
TA = –40°C
to +85°C
Units
Min.
Typ.
Max.
Min.
Max.
tPLH, tPHL
Propagation Delay Time
to Q1
3.3 ± 0.3
CL = 15pF
7.5
11.9
1.0
14.0
ns
CL = 50pF
10.0
15.4
1.0
17.5
5.0 ± 0.5
CL = 15pF
4.8
7.3
1.0
8.5
ns
CL = 50pF
6.3
9.3
1.0
10.5
tPLH, tPHL
Propagation Delay Time
between Stages from
Qn to Qn+1
3.3 ± 0.3
CL = 15pF
ns
CL = 50pF
2.4
4.4
1.0
5.0
5.0 ± 0.5
CL = 15pF
ns
CL = 50pF
1.6
3.1
1.0
3.5
tPHL
Propagation Delay Time
MR–Qn
3.3 ± 0.3
CL = 15pF
8.3
12.8
1.0
15.0
ns
CL = 50pF
10.8
16.3
1.0
18.5
5.0 ± 0.5
CL = 15pF
5.6
8.6
1.0
10.0
ns
CL = 50pF
7.1
10.6
1.0
12.0
fMAX
Maximum Clock
Frequency
3.3 ± 0.3
CL = 15pF
90
140
75
MHz
CL = 50pF
55
80
50
5.0 ± 0.5
CL = 15pF
150
210
125
MHz
CL = 50pF
95
125
80
CIN
Input Capacitance
VCC = Open
4
10
pF
CPD
Power Dissipation
Capacitance
(2)
21
pF
Symbol
Parameter
VCC (V)
TA = 25°C
TA = –40°C
to +85°C
Units
Typ.
Guaranteed Minimum
tw(L), tw(H)
Minimum Pulse Width (CP)
3.3 ± 0.3
5.0
ns
5.0 ± 0.5
5.0
tw(L)
Minimum Pulse Width (MR)
3.3 ± 0.3
5.0
ns
5.0 ± 0.5
5.0
tREC
Minimum Removal Time (MR)
3.3 ± 0.3
5.0
ns
5.0 ± 0.5
5.0
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