參數(shù)資料
型號(hào): 74VHC273
廠商: Fairchild Semiconductor Corporation
英文描述: Octal D-Type Flip-Flop
中文描述: 八路D類觸發(fā)器
文件頁數(shù): 4/10頁
文件大?。?/td> 72K
代理商: 74VHC273
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
Unit
T
A
= 25
o
C
Min.
Typ.
-40 to 85
o
C
Min.
Max.
10
Max.
10
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note 1)
4
pF
pF
31
1)C
PD
isdefined as thevalue oftheIC’sinternal equivalent capacitance whichiscalculated fromtheoperatingcurrent consumption without load.(Referto
TestCircuit).Average operatingcurrent canbeobtained bythefollowingequation.I
CC
(opr)=C
PD
V
CC
f
IN
+I
CC
/8(per Flip-Flop)
AC ELECTRICAL CHARACTERISTICS
(Inputt
r
= t
f
=3 ns)
Symbol
Parameter
Test Condition
C
L
(pF)
3.3
(*)
15
3.3
(*)
50
5.0
(**)
5.0
(**)
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
3.3
(*)
50
5.0
(**)
50
Value
Unit
V
CC
(V)
T
A
= 25
o
C
Min.
Typ.
-40 to 85
o
C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
13.6
17.1
9.0
11.0
13.6
17.1
8.5
10.5
5.0
5.0
5.5
5.0
5.5
4.5
1.0
1.0
2.5
2.0
Max.
16.0
19.5
10.5
12.5
16.0
19.5
10.0
12.0
6.0
5.0
6.5
5.0
6.5
4.5
1.0
1.0
2.5
2.0
t
PLH
t
PHL
Propagation Delay
Time
CK to Q
8.7
11.2
5.8
7.3
8.9
11.4
5.2
6.7
ns
15
50
15
50
15
50
t
PHL
Propagation Delay
Time
CLR to Q
ns
t
w
CLR pulse Width
LOW
ns
t
w
CK pulse Width
HIGH or LOW
ns
t
s
Setup Time D to CK
HIGH or LOW
ns
t
h
Hold Time D to CK
HIGH or LOW
ns
t
REM
Removal Time
CLR to CK
ns
f
MAX
Maximum Clock
Frequency
15
50
15
50
75
50
120
80
120
75
165
110
65
45
100
70
MHz
t
OSLH
t
OSHL
Output to Output Skew
Time (note 1)
(*) Voltagerangeis3.3V
±
0.3V
(**) Voltagerange is 5V
±
0.5V
Note1:Parameter guaranteed bydesign. t
soLH
=|t
pLHm
-t
pLHn
|,t
soHL
=|t
pHLm
-t
pHLn
|
1.5
1.0
1.5
1.0
ns
74VHC273
4/10
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