參數(shù)資料
型號(hào): 74VHC240M
廠商: Fairchild Semiconductor
文件頁數(shù): 5/9頁
文件大?。?/td> 0K
描述: IC INVERTER DUAL 4-INPUT 20SOIC
標(biāo)準(zhǔn)包裝: 1,080
系列: 74VHC
邏輯類型: 逆變器,緩沖器
電路數(shù): 2
輸入數(shù): 4
特點(diǎn): 三態(tài)
電源電壓: 2 V ~ 5.5 V
電流 - 靜態(tài)(最大值): 4µA
輸出電流高,低: 8mA,8mA
邏輯電平 - 低: 0.5V
邏輯電平 - 高: 1.5V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 7.5ns @ 5V,50pF
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 20-SOIC
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 管件
74VHC240
Octal
Buff
er/Line
Driver
with
3-ST
A
TE
Outputs
1992 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC240 Rev. 1.3
5
AC Electrical Characteristics
Notes:
3. Parameter guaranteed by design. tOSLH = |tPLHmax – tPLHmin|; tOSHL = |tPHLmax – tPHLmin|
4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
ICC (opr.) = CPD VCC fIN + ICC / 8 (per bit).
Symbol
Parameter
VCC (V)
Conditions
TA = 25°C
TA = –40°C
to +85°C
Units
Min.
Typ.
Max.
Min.
Max.
tPLH, tPHL Propagation Delay
Time
3.3 ± 0.3
CL = 15pF
5.3
7.5
1.0
9.0
ns
CL = 50pF
7.8
11.0
1.0
12.5
5.0 ± 0.5
CL = 15pF
3.6
5.5
1.0
6.5
CL = 50pF
5.1
7.5
1.0
8.5
tPZL, tPZH 3-STATE Output
Enable Time
3.3 ± 0.3 RL = 1k
CL = 15pF
6.6
10.6
1.0
12.5
ns
CL = 50pF
9.1
14.1
1.0
16.0
5.0 ± 0.5
CL = 15pF
4.7
7.3
1.0
8.5
CL = 50pF
6.2
9.3
1.0
10.5
tPLZ, tPHZ 3-STATE Output
Disable Time
3.3 ± 0.3 RL = 1k
CL = 50pF
10.3
14.0
1.0
16.0
ns
5.0 ± 0.5
CL = 50pF
6.7
9.2
1.0
10.5
tOSLH,
tOSHL
Output to Output
Skew
3.3 ± 0.3 (3)
CL = 50pF
1.5
ns
5.0 ± 0.5
CL = 50pF
1.0
CIN
Input Capacitance
VCC = Open
4
10
pF
COUT
Output Capacitance
VCC = 5.0V
6
pF
CPD
Power Dissipation
Capacitance
(4)
17
pF
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