參數(shù)資料
型號(hào): 74VHC175SJ
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Quad D-Type Flip-Flop
中文描述: AHC/VHC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
封裝: 5.30 MM, EIAJ TYPE2, SOP-16
文件頁數(shù): 1/7頁
文件大?。?/td> 71K
代理商: 74VHC175SJ
August 1993
Revised April 1999
7
1999 Fairchild Semiconductor Corporation
DS011637.prf
www.fairchildsemi.com
74VHC175
Quad D-Type Flip-Flop
General Description
The VHC175 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The VHC175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D inputs is stored during the LOW-to-HIGH clock transition.
Both true and complemented outputs of each flip-flop are
provided. A Master Reset input resets all flip-flops, inde-
pendent of the Clock or D inputs, when LOW.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
I
High Speed: f
MAX
=
210 MHz (typ) at V
CC
=
5V
I
Low power dissipation: I
CC
=
4
μ
A (max) at T
A
=
25
°
C
I
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
I
Power down protection is provided on all inputs
I
Low noise: V
OLP
=
0.8V (max)
I
Pin and function compatible with 74HC175
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Logic Symbols
IEEE/IEC
Order Number
74VHC175M
74VHC175SJ
74VHC175MTC
74VHC175N
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Description
D
0
–D
3
CP
Data Inputs
Clock Pulse Input
MR
Master Reset Input
Q
0
–Q
3
Q
0
–Q
3
True Outputs
Complement Outputs
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