參數(shù)資料
型號(hào): 74VHC174M
廠商: 意法半導(dǎo)體
英文描述: Quadruple 2-Input Positive-NOR Gates 14-TSSOP -40 to 85
中文描述: 四2正輸入或非門 14-TSSOP封裝;-40℃到85℃
文件頁數(shù): 4/10頁
文件大?。?/td> 71K
代理商: 74VHC174M
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
Unit
T
A
= 25
o
C
Min.
Typ.
-40 to 85
o
C
Min.
Max.
10
Max.
10
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note 1)
4
pF
pF
29
1)C
PD
isdefined as thevalue oftheIC’sinternal equivalent capacitance whichiscalculated fromtheoperatingcurrent consumption without load.(Referto
TestCircuit).Average operatingcurrent canbeobtained bythefollowingequation.I
CC
(opr)=C
PD
V
CC
f
IN
+I
CC
/6(per Flip-Flop)
AC ELECTRICAL CHARACTERISTICS
(Inputt
r
= t
f
=3 ns)
Symbol
Parameter
Test Condition
C
L
(pF)
3.3
(*)
15
3.3
(*)
50
5.0
(**)
15
5.0
(**)
50
3.3
(*)
15
3.3
(*)
50
5.0
(**)
15
5.0
(**)
50
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
15
3.3
(*)
50
5.0
(**)
15
5.0
(**)
50
Value
Unit
V
CC
(V)
T
A
= 25
o
C
Min.
Typ.
-40 to 85
o
C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
11.0
14.5
7.2
9.2
11.4
14.9
7.6
9.6
5.0
5.0
5.0
5.0
5.0
4.5
0.0
0.5
3.0
2.5
Max.
13.0
16.5
8.5
10.5
13.5
17.0
9.0
11.0
5.0
5.0
5.0
5.0
6.0
4.5
0.0
0..5
3.0
2.5
t
PLH
t
PHL
Propagation Delay Time
CKto Q
7.2
9.7
4.9
6.4
7.4
9.9
5.1
6.6
ns
t
PHL
Propagation Delay Time
CLRto Q
ns
t
w
CLRpulseWidth
LOW
ns
t
w
CKpulse Width
HIGHr LOW
ns
t
s
SetupTime D to CK
HIGHorLOW
ns
t
h
Hold TimeD to CK
HIGHorLOW
ns
t
REM
Removal Time
CLRto CK
ns
f
MAX
Maximum Clock
Frequency
95
55
130
90
150
85
175
120
80
50
110
80
MHz
(*) Voltagerangeis3.3V
±
0.3V
(**) Voltagerange is 5V
±
0.5V
74VHC174
4/10
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