參數(shù)資料
型號(hào)： 74VHC161SJX
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 8/11頁(yè)
文件大?。?/td> 0K
描述： IC COUNTER BINARY 4BIT 16SOP
標(biāo)準(zhǔn)包裝： 2,000
系列： 74VHC
邏輯類型： 二進(jìn)制計(jì)數(shù)器
方向： 上
元件數(shù)： 1
每個(gè)元件的位元數(shù)： 4
復(fù)位： 異步
計(jì)時(shí)： 同步
計(jì)數(shù)速率： 125MHz
觸發(fā)器類型： 正邊沿
電源電壓： 2 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOP
包裝： 帶卷 (TR)
74VHC161
4-Bit
Binar
y
Counter
with
Async
hr
onous
Clear
1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC161 Rev. 1.4
6
AC Electrical Characteristics
Note:
3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
ICC (opr) = CPD VCC fIN + ICC
When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ICC which is obtained
from the following formula:
CQ0–CQ3 and CTC are the capacitances at Q0–Q3 and TC, respectively. FCP is the input frequency of the CP.
Symbol
Parameter
VCC (V)
Conditions
TA = 25°C
TA = –40° to
+85°C
Units
Min.
Typ.
Max.
Min.
Max.
tPLH, tPHL
Propagation Delay
Time (CP–Qn)
3.3 ± 0.3
CL = 15pF
8.3
12.8
1.0
15.0
ns
CL = 50pF
10.8
16.3
1.0
18.5
5.0 ± 0.5
CL = 15pF
4.9
8.1
1.0
9.5
ns
CL = 50pF
6.4
10.1
1.0
11.5
tPLH, tPHL
Propagation Delay
Time (CP–TC, Count)
3.3 ± 0.3
CL = 15pF
8.7
13.6
1.0
16.0
ns
CL = 50pF
11.2
17.1
1.0
19.5
5.0 ± 0.5
CL = 15pF
4.9
8.1
1.0
9.5
ns
CL = 50pF
6.4
10.1
1.0
11.5
tPLH, tPHL
Propagation Delay
Time (CP–TC, Load)
3.3 ± 0.3
CL = 15pF
11.0
17.2
1.0
20.0
ns
CL = 50pF
13.5
20.7
1.0
23.5
5.0 ± 0.5
CL = 15pF
6.2
10.3
1.0
12.0
ns
CL = 50pF
7.7
12.3
1.0
14.0
tPLH, tPHL
Propagation Delay
Time (CET–TC)
3.3 ± 0.3
CL = 15pF
7.5
12.3
1.0
14.5
ns
CL = 50pF
10.5
15.8
1.0
18.0
5.0 ± 0.5
CL = 15pF
4.9
8.1
1.0
9.5
ns
CL = 50pF
6.4
10.1
1.0
11.5
tPHL
Propagation Delay
Time (MR –Qn)
3.3 ± 0.3
CL = 15pF
8.9
13.6
1.0
16.0
ns
CL = 50pF
11.2
17.1
1.0
19.5
5.0 ± 0.5
CL = 15pF
5.5
9.0
1.0
10.5
ns
CL = 50pF
7.0
11.0
1.0
12.5
tPHL
Propagation Delay
Time (MR –TC)
3.3 ± 0.3
CL = 15pF
8.4
13.2
1.0
15.5
ns
CL = 50pF
10.9
16.7
1.0
19.0
5.0 ± 0.5
CL = 15pF
5.0
8.6
1.0
10.0
ns
CL = 50pF
6.5
10.6
1.0
12.0
fMAX
Maximum Clock
Frequency
3.3 ± 0.3
CL = 15pF
80
130
70
MHz
CL = 50pF
55
85
50
5.0 ± 0.5
CL = 15pF
135
185
115
MHz
CL = 50pF
95
125
85
CIN
Input Capacitance
VCC = Open
4
10
pF
CPD
Power Dissipation
Capacitance
(3)
23
pF
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