參數(shù)資料
型號: 74VHC125SJ
廠商: Fairchild Semiconductor
文件頁數(shù): 5/9頁
文件大?。?/td> 0K
描述: IC BUFF TRI-ST QD N-INV 14SOP
標(biāo)準(zhǔn)包裝: 47
系列: 74VHC
邏輯類型: 緩沖器/線路驅(qū)動器,非反相
元件數(shù): 4
每個元件的位元數(shù): 1
輸出電流高,低: 8mA,8mA
電源電壓: 2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 管件
1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC125 Rev. 1.4.0
5
74VHC125
Quad
Buff
er
with
3-ST
A
TE
Outputs
AC Electrical Characteristics
Notes:
3. Parameter guaranteed by design. tOSLH = |tPLHmax – tPLHmin|; tOSHL = |tPHLmax – tPHLmin|.
4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
ICC (Opr.) = CPD VCC fIN + ICC / 4 (per bit).
Symbol
Parameter
VCC (V)
Conditions
TA = 25°C
TA = –40°C
to +85°C
Units
Min.
Typ.
Max.
Min.
Max.
tPLH, tPHL
Propagation Delay
Time
3.3 ± 0.3
CL = 15pF
5.6
8.0
1.0
9.5
ns
CL = 50pF
8.1
11.5
1.0
13.0
5.0 ± 0.5
CL = 15pF
3.8
5.5
1.0
6.5
ns
CL = 50pF
5.3
7.5
1.0
8.5
tPZL, tPZH
3-STATE Output
Enable Time
3.3 ± 0.3
RL = 1k CL = 15pF
5.4
8.0
1.0
9.5
ns
CL = 50pF
7.9
11.5
1.0
13.0
5.0 ± 0.5
CL = 15pF
3.6
5.1
1.0
6.0
ns
CL = 50pF
5.1
7.1
1.0
8.0
tPLZ, tPHZ
3-STATE Output
Disable Time
3.3 ± 0.3
RL = 1k CL = 50pF
13.2
1.0
15.0
ns
5.0 ± 0.5
CL = 50pF
6.1
8.8
1.0
10.0
tOSLH, tOSHL Output to Output
Skew
3.3 ± 0.3
(3)
CL = 50pF
1.5
ns
5.0 ± 0.5
CL = 50pF
1.0
CIN
Input Capacitance
VCC = Open
4
10
pF
COUT
Output Capacitance
VCC = 5.0V
6
pF
CPD
Power Dissipation
Capacitance
(4)
14
pF
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