參數(shù)資料
型號: 74VHC00
廠商: 意法半導(dǎo)體
英文描述: QUAD 2-INPUT NAND GATE
中文描述: 四2輸入與非門
文件頁數(shù): 1/7頁
文件大?。?/td> 53K
代理商: 74VHC00
74VHC00
QUAD 2-INPUT NAND GATE
PRELIMINARY DATA
June 1999
I
HIGHSPEED:t
PD
=3.7ns(TYP.)atV
CC
= 5V
I
LOWPOWERDISSIPATION:
I
CC
=2
μ
A(MAX.) at T
A
=25
o
C
I
HIGHNOISEIMMUNITY:
V
NIH
= V
NIL
=28%V
CC
(MIN.)
I
POWERDOWN PROTECTIONON INPUTS
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 8 mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 2Vto 5.5V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES00
I
IMPROVEDLATCH-UP IMMUNITY
I
LOWNOISE:V
OLP
= 0.8V(Max.)
DESCRIPTION
The 74VHC00 is an advancedhigh-speed CMOS
QUAD 2-INPUT NAND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface5V to 3V.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2kV ESD immunity and transient excess
voltage.
equipped with
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES :
74VHC00M
74VHC00T
M
(Micro Package)
T
(TSSOPPackage)
1/7
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74VHC00TTR QUAD 2-INPUT NAND GATE
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