參數(shù)資料
型號: 74VCXH16374MTD
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Low Voltage 16-Bit D-Type Flip-Flop with Bushold
中文描述: ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48
封裝: 6.10 MM, MO-153AB, TSSOP-48
文件頁數(shù): 6/12頁
文件大?。?/td> 285K
代理商: 74VCXH16374MTD
74VCXH16374
6/12
AC ELECTRICAL CHARACTERISTICS
(C
L
= 30pF, R
L
= 500
,
Input t
r
= t
f
= 2.0ns
)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the samedevice switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
1) C
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per
circuit)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
-40 to 85 °C
-55 to 125 °C
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time CK to Qn
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
2.3 to 2.7
3.0 to 3.6
1.0
0.8
1.0
0.8
1.0
0.8
1.5
1.5
1.0
1.0
1.5
1.5
200
250
3.9
3.0
4.6
3.5
3.8
3.5
1.0
0.8
1.0
0.8
1.0
0.8
1.5
1.5
1.0
1.0
1.5
1.5
180
235
4.7
3.5
5.1
4.3
4.6
4.3
ns
t
PZL
t
PZH
Output Enable Time
ns
t
PLZ
t
PHZ
Output Disable Time
ns
t
s
Setup TIme, HIGH or
LOW level Dn to CK
ns
t
h
Hold Time High or
LOW level Dn to CK
ns
t
w
CK Pulse Width,
HIGH
ns
f
MAX
Clock Pulse
Frequency
MHz
t
OSLH
t
OSHL
Output To Output
Skew Time (note1, 2)
0.5
0.5
0.5
0.5
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25 °C
Min.
Typ.
Max.
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
(note 1)
2.5 or 3.3
2.5 or 3.3
2.5 or 3.3
V
IN
= 0 or V
CC
V
IN
= 0 or V
CC
f
IN
= 10MHz
V
IN
= 0 or V
CC
6
7
20
pF
pF
pF
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PDF描述
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