參數(shù)資料
型號(hào): 74VCXH1632245TTR
廠商: 意法半導(dǎo)體
英文描述: 16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR WITH A SIDE SERIES RESISTOR
中文描述: 16位雙電源總線收發(fā)器電平轉(zhuǎn)換器與阿側(cè)的串聯(lián)電阻
文件頁(yè)數(shù): 1/17頁(yè)
文件大?。?/td> 272K
代理商: 74VCXH1632245TTR
1/17
June 2004
I
HIGH SPEED: t
PD
= 4.4ns (MAX.) at T
A
=85°C
V
CCA
= 3.0V V
CCB
= 2.3V
LOW POWER DISSIPATION:
I
CCA
= I
CCB
= 20
μ
A(MAX.) at T
A
=85°C
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OHA
| = I
OLA
= 8mA MIN at
V
CCA
= 3.0V; V
CCB
= 1.65V or 2.3V
|I
OHB
| = I
OLB
= 6mA (MIN at
V
CCA
= 2.3V or 3.0V; V
CCB
= 1.65V)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SERIES RESISTOR ON A SIDE
OPERATING VOLTAGE RANGE:
V
CCA
(OPR) = 2.3V to 3.6V (1.2V Data
Retention)
V
CCB
(OPR) = 1.65V to2.7V (1.2V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16245
BUS HOLD PROVIDED ON DATA INPUT
BOTH SIDE
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
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DESCRIPTION
The 74VCXH1632245 is a dual supply low voltage
CMOS 16-BIT BUS TRANSCEIVER fabricated
with sub-micron silicon gate and five-layer metal
wiring C
2
MOS technology. Designed for use as an
interface between a 3.3V bus and a 2.5V or 1.8V
bus in a mixed 3.3V/1.8V,3.3V/2.5V and 2.5V/
1.8V supply systems, it achieves high speed
operation while maintaining the CMOS low power
dissipation.
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
nDIR inputs. The enable inputs nG can be used to
disable the device so that the buses are effectively
isolated. The A-port interfaces with the 3V bus, the
B-port with the 2.5V and 1.8V bus.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD im-
munity and transient excess voltage. All floating
bus terminals during High Z State don’t need ex-
ternal pull-up or pull-down resistor.
74VCXH1632245
16-BIT DUAL SUPPLY BUS TRANSCEIVER
LEVEL TRANSLATOR WITH A SIDE SERIES RESISTOR
ORDER CODES
PACKAGE
T & R
TSSOP48
TFBGA54
μ
TFBGA42
74VCXH1632245TTR
74VCXH1632245LBR
74VCXH1632245TBR
TSSOP
μ
TFBGA
TFBGA
LOGIC DIAGRAM
n = 1, 2
Rev. 1
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