參數(shù)資料
型號: 74V1T126S
廠商: 意法半導(dǎo)體
英文描述: SINGLE BUS BUFFER 3-STATE
中文描述: 單總線緩沖器的三態(tài)
文件頁數(shù): 1/8頁
文件大?。?/td> 54K
代理商: 74V1T126S
74V1T126
SINGLE BUS BUFFER (3-STATE)
PRELIMINARY DATA
October 1999
I
HIGHSPEED:t
PD
=3.8ns(TYP.)atV
CC
= 5V
I
LOWPOWERDISSIPATION:
I
CC
=1
μ
A(MAX.) at T
A
=25
o
C
I
COMPATIBLEWITH TTL OUTPUTS:
V
IH
=2V (MIN),V
IL
= 0.8V(MAX)
I
POWERDOWN PROTECTIONON INPUT
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 8 mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 4.5Vto 5.5V
I
IMPROVEDLATCH-UP IMMUNITY
DESCRIPTION
The 74V1T126 is an advanced high-speed
CMOS SINGLE BUS BUFFER fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
3-STATE control input G has to be set LOW to
place the output into the high impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface5V to 3V.
PIN CONNECTION AND IEC LOGIC SYMBOLS
S
(SOT23-5L)
C
(SC-70)
ORDER CODE:
74V1T126S
74V1T126C
1/8
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