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參數(shù)資料
| 型號(hào)： | 74S225 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16 】 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS |
| 中文描述： | 16】5異步先入先出3記憶態(tài)輸出 |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大小： | 145K |
| 代理商： | 74S225 |
SN74S225
16
×
5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
VIH
VIL
Supply voltage
4.75
5
5.25
V
High-level input voltage
2
V
Low-level input voltage
0.8
V
IOH
High level output current
High-level output current
Q outputs
–6.5
mA
All other outputs
–3.2
IOL
Low level output current
Low-level output current
Q outputs
16
mA
All other outputs
8
TA
Operating free-air temperature
0
70
°
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
VCC = 4.75 V,
VCC = 4.75 V,
VCC = 4.75 V,
VCC = 4.75 V,
VCC = 4.75 V,
VCC = 5.25 V,
VCC = 5.25 V,
VCC = 5.25 V,
II = –18 mA
IOL = –6.5 mA
IOL = –3.2 mA
IOL = 16 mA
IOL = 8 mA
VO = 2.4 V
VO = 0.5 V
VI = 5.5 V
–1.2
V
VOH
Q outputs
2.4
2.9
V
All others
2.4
2.9
VOL
Q outputs
0.35
0.5
V
All others
0.35
0.5
IOZH
IOZL
II
50
μ
A
μ
A
mA
–50
1
IIH
Data
VCC= 5 25 V
VCC = 5.25 V,
VI= 2 7 V
VI = 2.7 V
40
μ
A
All others
25
IIL
Data
VCC= 5 25 V
VCC = 5.25 V,
VI= 0 5 V
VI = 0.5 V
–1
mA
All others
–0.25
IOS
ICC§
All typical values are at VCC = 5 V, TA = 25
°
C.
Duration of the short circuit should not exceed one second.
§ICC is measured with all inputs grounded and the outputs open.
VCC = 5.25 V,
VCC = 5.25 V
VO = 0
–30
–100
mA
80
120
mA
timing requirements over recommended operating conditions (unless otherwise noted) (see
Figure 1)
MIN
NOM
MAX
UNIT
fclock
Clock frequency
10
MHz
CLKA or CLKB high
25
tw
Pulse duration
UNCK IN low
7
ns
CLR low
40
tsu
Set p time before CLKA
Setup time before CLKA
↑
or CLKB
↑
Data (see Note 3)
–20
ns
CLR inactive
25
th
Hold time after CLKA
↑
or CLKB
↑
NOTE 3: Data must be set up within 20 ns after the load-clock positive transition.
70
ns
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