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參數(shù)資料
| 型號： | 74LVX573MTR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 301K |
| 代理商： | 74LVX573MTR |
1/13
August 2004
s
HIGH SPEED:
tPD=6.4ns (TYP.) at VCC = 3.3V
s
5V TOLERANT INPUTS
s
POWER-DOWN PROTECTION ON INPUTS
s
INPUT VOLTAGE LEVEL:
VIL = 0.8V, VIH = 2V at VCC =3V
s
LOW POWER DISSIPATION:
ICC = 4 A (MAX.) at TA=25°C
s
LOW NOISE:
VOLP = 0.3V (TYP.) at VCC =3.3V
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4 mA (MIN) at VCC = 3V
s
BALANCED PROPAGATION DELAYS:
tPLH tPHL
s
OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX573 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All
inputs
and
outputs
are
equipped
with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX573
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
74LVX573MTR
TSSOP
74LVX573TTR
TSSOP
SOP
Rev. 4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVX573MX | 功能描述:閉鎖 Octal Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVX573SJ | 功能描述:閉鎖 Octal Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVX573SJX | 功能描述:閉鎖 Octal Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVX573TTR | 功能描述:閉鎖 Octal "D" Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVX574M | 功能描述:觸發(fā)器 Oct D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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