參數(shù)資料
型號： 74LVX4245QSC
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： 8-Bit Dual Supply Translating Transceiver with TRI-STATE Outputs
中文描述： LV/LV-A/LVX/H SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24
封裝： 0.150 INCH, PLASTIC, SSOP-24
文件頁數(shù)： 1/13頁
文件大小： 309K
代理商： 74LVX4245QSC
1/13
August 2004
I
HIGH SPEED:
t
PD
= 8.5 ns (MAX.) at
V
CCA
=5.0V V
CCB
= 3.3V
LOW POWER DISSIPATION:
I
CCA
= I
CCB
=5
μ
A(MAX.) at T
A
=25°C
LOW NOISE: V
OLP
=0.3V (TYP.) at
V
CCA
=5.5V V
CCB
=3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CCA
(OPR) = 4.5V to 5.5V (1.2V Data Retention)
V
CCB
(OPR) = 2.7V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 4245
IMPROVED LATCH-UP IMMUNITY
I
I
I
I
I
I
DESCRIPTION
The 74LVX4245 is a dual supply low voltage
CMOS OCTAL BUS TRANSCEIVER fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology. Designed for use
as an interface between a 5V bus and a 3.3V bus
in a mixed 5V/3.3V supply systems, it achieves
high speed operation while maintaining the CMOS
low power dissipation.
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the buses are effectively
isolated.
The A-port interfaces with the 5V bus, the B-port
with the 3.3V bus.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
74LVX4245
OCTAL DUAL SUPPLY BUS TRANSCEIVER
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
TSSOP
74LVX4245MTR
74LVX4245TTR
TSSOP
SOP
Rev. 6
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