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參數(shù)資料
| 型號： | 74LVX161284MTDX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage IEEE 161284 Translating Transceiver |
| 中文描述： | 13 LINE TRANSCEIVER, PDSO48 |
| 封裝： | 6.10 MM, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 114K |
| 代理商： | 74LVX161284MTDX |
2005 Fairchild Semiconductor Corporation
DS500202
www.fairchildsemi.com
January 1999
Revised June 2005
7
74LVX161284
Low Voltage IEEE 161284 Translating Transceiver
General Description
The LVX161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in an
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (
r
14 mA) and are connected to a
separate power supply pin (V
CC
-cable) to allow these out-
puts to be driven by a higher supply voltage than the A-
side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an external cable. In addition, all inputs (except HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the V
CC
-cable supply to provide proper
termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A
1
–A
8
/B
1
–B
8
transceiver
pins.
Features
I
Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
I
Translation capability allows outputs on the cable side to
interface with 5V signals
I
All inputs have hysteresis to provide noise margin
I
B and Y output resistance optimized to drive external
cable
I
B and Y outputs in high impedance mode during power
down
I
Inputs and outputs on cable side have internal pull-up
resistors
I
Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
I
Replaces the function of two (2) 74ACT1284 devices
Ordering Code
Device also available in Tape and Reel. Specify by appending suffix letter
“
X
”
to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
74LVX161284MEA
74LVX161284MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
HD
DIR
A
1
–
A
8
B
1
–
B
8
A
9
–
A
13
Y
9
–
Y
13
A
14
–
A
17
C
14
–
C
17
PLH
IN
PLH
HLH
IN
HLH
Description
High Drive Enable Input (Active HIGH)
Direction Control Input
Inputs or Outputs
Inputs or Outputs
Inputs
Outputs
Outputs
Inputs
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
Host Logic HIGH Input
Host Logic HIGH Output
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| 74LVX16128A_YAC3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74LVX16240TTR | 功能描述:緩沖器和線路驅(qū)動器 16-Bit Bus Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| 74LVX16244TTR | 功能描述:緩沖器和線路驅(qū)動器 16-Bit Bus Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| 74LVX16245TTR | 功能描述:總線收發(fā)器 16-Bit Bus Transcvr RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVX16373TTR | 功能描述:閉鎖 16-Bit "D" Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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