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參數(shù)資料
| 型號： | 74LVX161284MEA |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX TRANSL LV IEEE 48-SSOP |
| 產(chǎn)品變化通告： | Die Material/Mold Compound Change 10/Sept/2008 |
| 標(biāo)準(zhǔn)包裝： | 29 |
| 系列： | 74LVX |
| 邏輯類型： | IEEE STD 1284 轉(zhuǎn)換收發(fā)器 |
| 電源電壓： | 3 V ~ 3.6 V |
| 位數(shù)： | 8 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 管件 |
2005 Fairchild Semiconductor Corporation
DS500202
www.fairchildsemi.com
January 1999
Revised June 2005
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74LVX161284
Low Voltage IEEE 161284 Translating Transceiver
General Description
The LVX161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in an
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (
r 14 mA) and are connected to a
separate power supply pin (VCC-cable) to allow these out-
puts to be driven by a higher supply voltage than the A-
side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an external cable. In addition, all inputs (except HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the VCC-cable supply to provide proper
termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A1–A8/B1–B8 transceiver
pins.
Features
s Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
s Translation capability allows outputs on the cable side to
interface with 5V signals
s All inputs have hysteresis to provide noise margin
s B and Y output resistance optimized to drive external
cable
s B and Y outputs in high impedance mode during power
down
s Inputs and outputs on cable side have internal pull-up
resistors
s Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
s Replaces the function of two (2) 74ACT1284 devices
Ordering Code
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74LVX161284MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVX161284MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
HD
High Drive Enable Input (Active HIGH)
DIR
Direction Control Input
A1–A8
Inputs or Outputs
B1–B8
Inputs or Outputs
A9–A13
Inputs
Y9–Y13
Outputs
A14–A17
Outputs
C14–C17
Inputs
PLHIN
Peripheral Logic HIGH Input
PLH
Peripheral Logic HIGH Output
HLHIN
Host Logic HIGH Input
HLH
Host Logic HIGH Output
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVX161284MEA.DEL | 制造商:Fairchild Semiconductor Corporation 功能描述:Translating Transceiver 13TX 12RX 48-Pin SSOP W Rail 制造商:Fairchild Semiconductor Corporation 功能描述:IEEE 1284 Transceiver 13TX 12RX 48-Pin SSOP W Rail |
| 74LVX161284MEA_Q | 功能描述:轉(zhuǎn)換 - 電壓電平 IEEE 161284 Trans RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| 74LVX161284MEAX | 功能描述:轉(zhuǎn)換 - 電壓電平 IEEE 161284 Trans RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| 74LVX161284MEAX | 制造商:Fairchild Semiconductor Corporation 功能描述:TRANSCEIVER LOGIC IC |
| 74LVX161284MTD | 功能描述:轉(zhuǎn)換 - 電壓電平 IEEE 161284 Trans RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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