參數(shù)資料
型號(hào): 74LVX125SJ
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類(lèi): 通用總線功能
英文描述: Low Voltage Quad Buffer with 3-STATE Outputs
中文描述: LV/LV-A/LVX/H SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
封裝: 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-14
文件頁(yè)數(shù): 4/12頁(yè)
文件大?。?/td> 227K
代理商: 74LVX125SJ
74LVX125
4/12
Table 8: AC Electrical Characteristics
(Input t
r
= t
f
= 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
Table 9: Capacitive Characteristics
1) C
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/4 (per circuit)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
2.7
2.7
3.3
(*)
3.3
(*)
2.7
2.7
3.3
(*)
3.3
(*)
2.7
3.3
(*)
2.7
15
50
15
5.8
8.3
4.4
10.1
13.6
6.2
1.0
1.0
1.0
13.5
17.0
8.5
1.0
1.0
1.0
14.5
18.0
9.5
ns
50
15
50
15
6.9
5.3
7.8
4.0
9.7
9.3
12.8
5.6
1.0
1.0
1.0
1.0
12.0
12.5
16.0
7.5
1.0
1.0
1.0
1.0
13.0
13.5
17.0
8.5
t
PZL
t
PZH
Output Enable
Time
ns
50
50
50
50
6.5
10.0
8.3
0.5
9.1
15.7
11.2
1.0
1.0
1.0
1.0
11.0
19.0
13.0
1.5
1.0
1.0
1.0
12.0
20.0
14.0
1.5
t
PLZ
t
PHZ
Output Disable
Time
ns
t
OSLH
t
OSHL
Output to Output
Skew Time (note
1,2)
ns
3.3
(*)
50
0.5
1.0
1.5
1.5
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
C
OUT
Input Capacitance
Output
Capacitance
Power Dissipation
Capacitance
(note 1)
3.3
4
10
10
10
pF
3.3
6
pF
C
PD
3.3
14
pF
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