參數(shù)資料
型號: 74LVTH374SJX
廠商: Fairchild Semiconductor
文件頁數(shù): 3/10頁
文件大?。?/td> 0K
描述: IC FLIP FLOP OCT D 3ST 20SOP
標(biāo)準(zhǔn)包裝: 2,000
系列: 74LVTH
功能: 標(biāo)準(zhǔn)
類型: D 型總線
輸出類型: 三態(tài)非反相
元件數(shù): 1
每個元件的位元數(shù): 8
頻率 - 時鐘: 160MHz
延遲時間 - 傳輸: 4.8ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 32mA,64mA
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
1999 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVT374, 74LVTH374 Rev. 1.5.0
2
74L
VT374,
74L
VTH374
Lo
w
V
olta
g
e
Octal
D-T
ype
Flip-Flop
with
3-ST
A
TE
Outputs
Connection Diagram
Pin Description
Functional Description
The LVT374 and LVTH374 consist of eight edge-
triggered flip-flops with individual D-type inputs and
3-STATE true outputs. The buffered clock and buffered
Output Enable are common to all flip-flops. The eight flip-
flops will store the state of their individual D inputs that
meet the setup and hold time requirements on the LOW-
to-HIGH Clock (CP) transition. With the Output Enable
(OE) LOW, the contents of the eight flip-flops are avail-
able at the outputs. When the OE is HIGH, the outputs
go to the high impedance state. Operation of the OE
input does not affect the state of the flip-flops.
Logic Symbols
IEEE/IEC
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Z
= High Impedance
= LOW-to-HIGH Transition
Oo = Previous Oo before HIGH-to-LOW of CP
Pin Names
Description
D0–D7
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
O0–O7
3-STATE Outputs
Inputs
Outputs
Dn
CP
OE
On
HL
H
LL
L
XL
L
Oo
XX
H
Z
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