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參數(shù)資料
| 型號： | 74LVTH32244 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Low Voltage 32-Bit Buffer/Line Driver with 3-STATE Outputs (Preliminary) |
| 中文描述： | 低電壓32位緩沖器/線與三態(tài)輸出驅(qū)動器（初步） |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 64K |
| 代理商： | 74LVTH32244 |
Preliminary
2001 Fairchild Semiconductor Corporation
DS500434
www.fairchildsemi.com
January 2001
Revised August 2001
7
74LVT32244
74LVTH32244
Low Voltage 32-Bit Buffer/Line Driver
with 3-STATE Outputs (Preliminary)
General Description
The LVT32244 and LVTH32244 contain thirty-two non-
inverting buffers with 3-STATE outputs designed to be
employed as a memory and address driver, clock driver, or
bus oriented transmitter/receiver. The device is nibble con-
trolled. Individual 3-STATE control inputs can be shorted
together for 8-bit, 16-bit, or 32-bit operation.
The LVTH32244 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) V
CC
applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT32244 and
LVTH32244 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation
Features
I
Input and output interface capability to systems at
5V V
CC
I
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH32244),
also available without bushold feature (74LVT32244).
I
Live insertion/extraction permitted
I
Power Up/Down high impedance provides glitch-free
bus loading
I
Outputs source/sink
32 mA/
+
64 mA
I
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
I
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
(Preliminary)
Ordering Code:
Note 1:
BGA package available in Tape and Reel only.
Logic Symbol
Order Number
74LVT32244GX
(Note 1)
74LVTH32244GX
(Note 1)
Package Number
BGA96A
(Preliminary)
BGA96A
(Preliminary)
Package Description
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
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| 74LVT32244GX | Low Voltage 32-Bit Buffer/Line Driver with 3-STATE Outputs (Preliminary) |
| 74LVTH32244GX | Low Voltage 32-Bit Buffer/Line Driver with 3-STATE Outputs (Preliminary) |
| 74LVT32245 | Low Voltage 32-Bit Transceiver with 3-STATE Outputs |
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| 74LVTH32245G | Quadruple Positive-NOR Gates With Schmitt-Trigger Inputs 14-PDIP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVTH32245EC | 功能描述:總線收發(fā)器 3.3V 32-BIT XCEIVER DIR PIN RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH32245EC,518 | 功能描述:總線收發(fā)器 3.3V 32-BIT XCEIVER RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH32245EC,551 | 功能描述:總線收發(fā)器 3.3V 32-BIT XCEIVER RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH32245EC,557 | 功能描述:總線收發(fā)器 3.3V 32-BIT XCEIVER RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH32245EC-S | 功能描述:總線收發(fā)器 3.3V 32-BIT XCEIVER DIR PIN RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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