參數(shù)資料
型號(hào)： 74LVT574WM
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： 8-Bit Binary Counters With 3-State Output Registers 16-SOIC -40 to 85
中文描述： LVT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
封裝： 0.300 INCH, MS-013, SOIC-20
文件頁數(shù)： 5/12頁
文件大?。?/td> 98K
代理商： 74LVT574WM
Philips Semiconductors
Product specification
74LVT574
3.3V Octal D-type flip-flop (3-State)
1998 Feb 19
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
°
C to +85
°
C
MIN
TYP
1
–0.9
V
CC
-0.2
V
CC
-0.1
2.4
2.0
UNIT
MAX
–1.2
V
IK
Input clamp voltage
V
CC
= 2.7V; I
IK
= –18mA
V
CC
= 2.7 to 3.6V; I
OH
= –100
μ
A
V
CC
= 2.7V; I
OH
= –8mA
V
CC
= 3.0V; I
OH
= –32mA
V
CC
= 2.7V; I
OL
= 100
μ
A
V
CC
= 2.7V; I
OL
= 24mA
V
CC
= 3.0V; I
OL
= 16mA
V
CC
= 3.0V; I
OL
= 32mA
V
CC
= 3.0V; I
OL
= 64mA
V
CC
= 3.6V; I
O
= 1mA; V
I
= GND or V
CC
V
CC
= 0 or 3.6V; V
I
= 5.5V
V
CC
= 3.6V; V
I
= V
CC
or GND
V
CC
= 3.6V; V
I
= V
CC
V
CC
= 3.6V; V
I
= 0
V
CC
= 0V; V
I
or V
O
= 0 to 4.5V
V
CC
= 3V; V
I
= 0.8V
V
CC
= 3V; V
I
= 2.0V
V
CC
= 0V to 3.6V; V
CC
= 3.6V
V
V
OH
High-level output voltage
2.5
2.2
0.1
0.3
0.25
0.3
0.4
0.13
1
±
0.1
0.1
–1
1
150
–150
V
0.2
0.5
0.4
0.5
0.55
0.55
10
±
1
1
-5
±
100
V
OL
Low-level output voltage
V
V
RST
Power-up output low voltage
5
V
I
I
Input leakage current
In ut leakage current
Control pins
μ
A
Data pins
Data ins
4
I
OFF
Output off current
μ
A
75
–75
±
500
I
HOLD
Bus Hold current A inputs
7
μ
A
I
EX
Current into an output in the
High state when V
O
> V
CC
Power up/down 3-State output
current
3
3-State output High current
3-State output Low current
V
O
= 5.5V; V
CC
= 3.0V
60
125
μ
A
I
PU/PD
V
≤
1.2V; V
= 0.5V to V
CC
; V
I
= GND or V
CC
;
OE/OE = Don’t care
V
CC
= 3.6V; V
O
= 3V; V
I
= V
IL
or V
IH
V
CC
= 3.6V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 3.6V; Outputs High, V
I
= GND or V
CC,
I
O =
0
V
CC
= 3.6V; Outputs Low, V
I
= GND or V
CC,
I
O =
0
V
CC
= 3.6V; Outputs Disabled; V
I
= GND or V
CC,
I
O =
0
5
V
= 3V to 3.6V; One input at V
CC
-0.6V,
Other inputs at V
CC
or GND
1
±
100
μ
A
I
OZH
I
OZL
I
CCH
I
CCL
I
CCZ
1
1
5
–5
0.19
12
0.19
μ
A
μ
A
0.13
3
0.13
Quiescent supply current
3
mA
I
CC
Additional supply current per
input pin
2
0.1
0.2
mA
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
°
C.
2. This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND
3. This parameter is valid for any V
CC
between 0V and 1.2V with a transition time of up to 10msec. From V
CC
= 1.2V to V
CC
= 3.3V
±
0.3V a
transition time of 100
μ
sec is permitted. This parameter is valid for T
amb
= 25
°
C only.
4. Unused pins at V
CC
or GND.
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
6. I
is measured with outputs pulled to V
or GND.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
; T
amb
= –40
°
C to +85
°
C.
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V
±
0.3V
TYP
1
V
CC
= 2.7V
MIN
150
UNIT
MIN
150
1.7
2.4
1.0
1.3
1.9
1.7
MAX
MAX
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum clock frequency
Propagation delay
CP to Qn
Output enable time
to High and Low level
Output disable time
from High and Low level
NO TAG
ns
NO TAG
3.6
4.3
2.9
3.4
4.0
3.2
5.4
5.9
4.8
5.1
5.5
4.5
6.2
6.6
5.9
6.2
5.9
4.5
ns
NO TAG
NO TAG
NO TAG
NO TAG
ns
ns
NOTE:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
°
C.
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