參數(shù)資料
型號: 74LVT2952PW,118
廠商: NXP Semiconductors
文件頁數(shù): 16/17頁
文件大小: 0K
描述: IC TRANSCVR 8BIT N-INV 24TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,500
系列: 74LVT
邏輯類型: 收發(fā)器,非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
輸出電流高,低: 32mA,64mA
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
其它名稱: 74LVT2952PW-T
74LVT2952PW-T-ND
935180870118
74LVT2952
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 11 September 2013
8 of 17
NXP Semiconductors
74LVT2952
3.3 V Octal registered transceiver; 3-State
[1]
Typical values are measured at Tamb =25 C and VCC = 3.3 V.
11. Waveforms
tsu(L)
set-up time LOW
An to CPAB or Bn to CPBA; see Figure 7
VCC = 2.7 V
3.0
-
ns
VCC = 3.3 V 0.3 V
2.5
1.0
-
ns
CEAB to CPAB or CEBA to CPBA; see Figure 7
VCC = 2.7 V
2.7
-
ns
VCC = 3.3 V 0.3 V
2.4
0.3
-
ns
th(H)
hold time HIGH
An to CPAB or Bn to CPBA; see Figure 7
VCC = 2.7 V
0.7
-
ns
VCC = 3.3 V 0.3 V
1.5
0.5
-
ns
CEAB to CPAB or CEBA to CPBA; see Figure 7
VCC = 2.7 V
0.7
-
ns
VCC = 3.3 V 0.3 V
2.5
0.3
-
ns
th(L)
hold time LOW
An to CPAB or Bn to CPBA; see Figure 7
VCC = 2.7 V
2.6
-
ns
VCC = 3.3 V 0.3 V
1.5
0.5
-
ns
CEAB to CPAB or CEBA to CPBA; see Figure 7
VCC = 2.7 V
2.6
-
ns
VCC = 3.3 V 0.3 V
2.5
0
-
ns
tW
pulse width
CPAB or CPBA; HIGH or LOW; see Figure 5
VCC = 2.7 V
3.3
-
ns
VCC = 3.3 V 0.3 V
3.3
1.0
-
ns
fmax
maximum frequency CPBA, CPAB; VCC = 3.3 V 0.3 V; see Figure 5
150
200
-
MHz
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 8.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Unit
Min
Typ[1]
Max
See Table 9 for measurement points
Fig 5.
Clock input to output propagation delay, clock pulse width and maximum frequency
aaa-008847
1/fmax
VM
GND
VI
VOH
VOL
VM
tW
tPHL
tPLH
tW
An or Bn
CPBA or
CPAB
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