參數(shù)資料
型號： 74LVT2952PW,112
廠商： NXP Semiconductors
文件頁數(shù)： 15/17頁
文件大小： 0K
描述： IC TRANSCVR 8BIT N-INV 24TSSOP
產(chǎn)品培訓(xùn)模塊： Logic Packages
標(biāo)準(zhǔn)包裝： 63
系列： 74LVT
邏輯類型： 收發(fā)器，非反相
元件數(shù)： 1
每個元件的位元數(shù)： 8
輸出電流高，低： 32mA，64mA
電源電壓： 2.7 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
其它名稱： 74LVT2952PW
74LVT2952PW-ND
935180870112
74LVT2952
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 11 September 2013
7 of 17
NXP Semiconductors
74LVT2952
3.3 V Octal registered transceiver; 3-State
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25 C.
[2]
For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
[3]
Unused pins at VCC or GND.
[4]
This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC =3.3 V 0.3 V
a transition time of 100 ms is permitted. This parameter is valid for Tamb = +25 C only.
[5]
This parameter is the bus hold overdrive current required to force the input to the opposite logic state.
[6]
This parameter is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
CI/O
input/output capacitance
at I/O data pins, outputs disabled;
VI/O =0V or3.0 V
-8
-
pF
Table 7.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Unit
Min
Typ[1]
Max
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 8.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Unit
Min
Typ[1]
Max
tPLH
LOW to HIGH
propagation delay
CPBA to An or CPAB to Bn; see Figure 5
VCC = 2.7 V
-
7.1
ns
VCC = 3.3 V 0.3 V
1.3
3.1
6.1
ns
tPHL
HIGH to LOW
propagation delay
CPBA to An or CPAB to Bn; see Figure 5
VCC = 2.7 V
-
6.9
ns
VCC = 3.3 V 0.3 V
1.8
3.8
6.0
ns
tPZH
OFF-state to HIGH
propagation delay
OEBA to An; OEAB to Bn; see Figure 7
VCC = 2.7 V
-
6.7
ns
VCC = 3.3 V 0.3 V
1.0
3.4
5.6
ns
tPZL
OFF-state to LOW
propagation delay
OEBA to An; OEAB to Bn; see Figure 7
VCC = 2.7 V
-
8.0
ns
VCC = 3.3 V 0.3 V
1.2
3.6
6.5
ns
tPHZ
HIGH to OFF-state
propagation delay
OEBA to An; OEAB to Bn; see Figure 7
VCC = 2.7 V
-
6.9
ns
VCC = 3.3 V 0.3 V
1.0
3.7
6.3
ns
tPLZ
LOW to OFF-state
propagation delay
OEBA to An; OEAB to Bn; see Figure 7
VCC = 2.7 V
-
5.3
ns
VCC = 3.3 V 0.3 V
1.6
3.4
5.1
ns
tsu(H)
set-up time HIGH
An to CPAB or Bn to CPBA; see Figure 7
VCC = 2.7 V
2.8
-
ns
VCC = 3.3 V 0.3 V
2.5
1.0
-
ns
CEAB to CPAB or CEBA to CPBA; see Figure 7
VCC = 2.7 V
0.8
-
ns
VCC = 3.3 V 0.3 V
0.9
0.3
-
ns
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