參數(shù)資料
型號: 74LVT245SJX
廠商: Fairchild Semiconductor
文件頁數(shù): 7/10頁
文件大小: 0K
描述: IC TRANSCVR TRI-ST 8BIT 20SOP
標(biāo)準(zhǔn)包裝: 2,000
系列: 74LVT
邏輯類型: 收發(fā)器,非反相
元件數(shù): 1
每個元件的位元數(shù): 8
輸出電流高,低: 32mA,64mA
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 帶卷 (TR)
1999 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVT245, 74LVTH245 Rev. 1.4.0
6
74L
VT245,
74L
VTH245
Lo
w
V
olta
g
e
Octal
Bidirectional
T
ransceiver
with
3-ST
A
TE
Inputs/Outputs
Physical Dimensions
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specications do not expand the terms of Fairchild’s worldwide terms and conditions,
specically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
0.10
C
A
SEE DETAIL A
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
PIN ONE
INDICATOR
0.25
1
10
B
C
A
M
20
11
B
X45
°
8
°
0
°
SEATING PLANE
GAGE PLANE
DETAIL A
SCALE: 2:1
SEATING PLANE
LAND PATTERN RECOMMENDATION
F) DRAWING FILENAME: MKT-M20BREV3
0.65
1.27
2.25
9.50
13.00
12.60
11.43
7.60
7.40
10.65
10.00
0.51
0.35
1.27
2.65 MAX
0.30
0.10
0.33
0.20
0.75
0.25
(R0.10)
1.27
0.40
(1.40)
0.25
D) CONFORMS TO ASME Y14.5M-1994
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