參數(shù)資料
型號: 74LVT16240MTDX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: 14-Stage Asynchronous Binary Counters And Oscillators 16-TSSOP -40 to 85
中文描述: LVT SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48
封裝: 6.10 MM, MO-153ED, TSSOP-48
文件頁數(shù): 1/6頁
文件大?。?/td> 105K
代理商: 74LVT16240MTDX
2005 Fairchild Semiconductor Corporation
DS012025
www.fairchildsemi.com
March 1999
Revised June 2005
7
74LVT16240
74LVTH16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVT16240 and LVTH16240 contain sixteen inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus-oriented
transmitter/receiver. The device is nibble controlled.
Individual 3-STATE control inputs can be shorted together
for 8-bit or 16-bit operation.
The LVTH16240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) V
CC
applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT16240 and
LVTH16240 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Features
I
Input and output interface capability to systems at
5V V
CC
I
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16240),
also available without bushold feature (74LVT16240)
I
Live insertion/extraction permitted
I
Power Up/Down high impedance provides glitch-free
bus loading
I
Outputs source/sink 32 mA/ 64 mA
I
Functionally compatible with the 74 series 16240
I
Latch-up performance exceeds 500 mA
I
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
Package
Number
MS48A
MTD48
MS48A
MTD48
Package Description
74LVT16240MEA
74LVT16240MTD
74LVTH16240MEA
74LVTH16240MTD
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
相關(guān)PDF資料
PDF描述
74LVTH16240 Octal Bus Transceivers With 3-State Outputs 20-SOIC -40 to 85
74LVTH16240MEA Octal Bus Transceivers With 3-State Outputs 20-SOIC -40 to 85
74LVTH16240MEAX Octal Bus Transceivers With 3-State Outputs 20-SOIC -40 to 85
74LVTH16240MTD Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
74LVTH16240MTDX Octal Bus Transceivers With 3-State Outputs 20-PDIP -40 to 85
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