參數(shù)資料
型號: 74LVT16240ADGG,512
廠商: NXP Semiconductors
文件頁數(shù): 6/10頁
文件大小: 0K
描述: IC BUFF DVR TRI-ST 16BIT 48TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 975
系列: 74LVT
邏輯類型: 逆變器,緩沖器
電路數(shù): 4
輸入數(shù): 4
特點: 三態(tài)
電源電壓: 2.7 V ~ 3.6 V
電流 - 靜態(tài)(最大值): 6mA
輸出電流高,低: 32mA,64mA
邏輯電平 - 低: 0.8V
邏輯電平 - 高: 2V
額定電壓和最大 CL 時的最大傳播延遲: 3.2ns @ 3.3V,50pF
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 48-TSSOP
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
包裝: 管件
其它名稱: 74LVT16240ADG
74LVT16240ADG-ND
935202860512
Philips Semiconductors
Product data
74LVT16240A
3.3 V 16-bit inverting buffer/driver (3-State)
2003 Feb 21
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = –40 °C to +85 °C
UNIT
MIN
TYP1
MAX
VIK
Input clamp voltage
VCC = 2.7 V; IIK = –18 mA
–0.85
1.2
V
VCC = 2.7 V to 3.6 V; IOH = –100 A
VCC–0.2
VCC
VOH
HIGH-level output voltage
VCC = 2.7 V; IOH = –8 mA
2.4
2.5
V
VCC = 3.0 V; IOH = –32 mA
2.0
2.3
VCC = 2.7 V; IOL = 100 A
0.07
0.2
VCC = 2.7 V; IOL = 24 mA
0.03
0.5
VOL
LOW-level output voltage
VCC = 3.0 V; IOL = 16 mA
0.25
0.4
V
VCC = 3.0 V; IOL = 32 mA
0.30
0.5
VCC = 3.0 V; IOL = 64 mA
0.40
0.55
VCC = 3.6 V; VI = VCC or GND
Control pins
0.1
±1.0
I
Input leakage current
VCC = 0 V or 3.6 V; VI = 5.5 V
0.4
10
A
II
Input leakage current
VCC = 3.6 V; VI = VCC
Data pins4
0.1
1
A
VCC = 3.6 V; VI = 0 V
Data pins4
–0.4
–5
IOFF
Output off current
VCC = 0 V; VI or VO = 0 V to 4.5 V
0.1
±100
A
6
VCC = 3 V; VI = 0.8 V
75
135
IHOLD
Bus Hold current A inputs6
VCC = 3 V; VI = 2.0 V
–75
–135
A
VCC = 0 V to 3.6 V; VCC = 3.6 V
±500
IEX
Current into an output in the
HIGH state when VO > VCC
VO = 5.5 V; VCC = 3.0 V
50
125
A
IPU/PD
Power-up/-down 3-State output
current3
VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC
OE/OE = Don’t care
1
±100
A
IOZH
3-State output HIGH current
VCC = 3.6 V; VO = 3.0 V; VI = VIL or VIH
0.5
5
A
IOZL
3-State output LOW current
VCC = 3.6 V; VO = 0.5 V; VI = VIL or VIH
0.5
–5
A
ICCH
VCC = 3.6 V; Outputs High, VI = GND or VCC, IO = 0
0.07
0.12
ICCL
Quiescent supply current
VCC = 3.6 V; Outputs Low, VI = GND or VCC, IO = 0
4.0
6.0
mA
ICCZ
VCC = 3.6 V; Outputs Disabled;
VI = GND or VCC, IO = 05
0.07
0.12
ICC
Additional supply current per
input pin2
VCC = 3V to 3.6V; One input at VCC–0.6V,
Other inputs at VCC or GND
0.1
0.20
mA
NOTES:
1. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
3. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 msec. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V
a transition time of 100
sec is permitted. This parameter is valid for Tamb = 25 °C only.
4. Unused pins at VCC or GND.
5. ICCZ is measured with outputs pulled to VCC or GND.
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
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