參數(shù)資料
型號(hào): 74LVQ240
廠商: 意法半導(dǎo)體
英文描述: Low Voltage Octal Bus Buffer with 3 State Outputs (Inverted)(低壓八總線緩沖器帶三態(tài)輸出)
中文描述: 低壓八路總線緩沖器的三態(tài)輸出(倒)(低壓八總線緩沖器帶三態(tài)輸出)
文件頁(yè)數(shù): 4/8頁(yè)
文件大小: 79K
代理商: 74LVQ240
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
Unit
V
CC
(V)
T
A
= 25
o
C
Min.
Typ.
-40 to 85
o
C
Min.
Max.
Max.
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (note 1)
1) C
PD
isdefined as the value ofthe IC’s internalequivalent capacitance which iscalculated fromtheoperating currentconsumption without load. (Refer to
Test Circuit).Average operting currentcan be obtained by the followingequation. I
CC
(opr) =C
PD
V
CC
f
IN
+I
CC
/n(percircuit)
3.3
3.3
3.3
5
10
15
pF
pF
pF
f
IN
=10MHz
TEST CIRCUIT
TEST
SWITCH
Open
2V
CC
GND
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
C
L
=50 pFor equivalent (includes jigand probe capacitance)
R
L
=R
1
=500
or equivalent
R
T
=Z
OUT
of pulse generator (typically50
)
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
=3ns)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
o
C
Min.
Typ.
-40 to 85
o
C
Min.
Max.
13
9
17
12
19
13.5
1.5
1.5
Max.
14
9.5
18
12.5
20
14
1.5
1.5
t
PLH
t
PHL
Propagation Delay Time
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
7
6
ns
t
PZL
t
PZH
Output Enable Time
8.5
7
9
7.5
0.5
0.5
ns
t
PLZ
t
PHZ
Output Disable Time
ns
t
OSLZ
t
OSHL
Output to Output Skew
Time (note 1, 2)
1) Skew isdefined as the absolute value of the difference between theactual propagation delay forany twooutputs ofthe samedevice switching in the
same direction, either HIGHor LOW
2) Parameter guaranteed bydesign
(*) Voltagerange is3.3V
±
0.3V
ns
74LVQ240
4/8
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