參數(shù)資料
型號: 74LVQ08SC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Low Voltage Quad 2-Input AND Gate
中文描述: LVQ SERIES, QUAD 2-INPUT AND GATE, PDSO14
封裝: 0.150 INCH, MS-012, SOIC-14
文件頁數(shù): 4/11頁
文件大小: 213K
代理商: 74LVQ08SC
74LVQ08
4/11
Table 8: AC Electrical Characteristics
(C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
= 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
Table 9: Capacitive Characteristics
1) C
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/4 (per gate)
Figure 3: Test Circuit
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= 500
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
2.7
3.3
(*)
2.7
3.3
(*)
.
6.8
5.6
0.5
0.5
12.0
8.5
1.0
1.0
13.0
9.0
1.0
1.0
15.0
10.5
1.0
1.0
ns
t
OSLH
t
OSHL
Output To Output
Skew Time
(note1, 2)
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(note 1)
3.3
4
pF
3.3
f
IN
= 10MHz
32
pF
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