參數(shù)資料
型號: 74LVCH322244AEC/G;
廠商: NXP Semiconductors
文件頁數(shù): 2/14頁
文件大?。?/td> 0K
描述: IC BUFF DVR TRI-ST 32BIT 96LFBGA
產(chǎn)品培訓模塊: Logic Packages
標準包裝: 1,425
系列: 74LVCH
邏輯類型: 緩沖器/線路驅(qū)動器,非反相
元件數(shù): 8
每個元件的位元數(shù): 4
輸出電流高,低: 12mA,12mA
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 96-LFBGA
供應商設備封裝: 96-LFBGA(13.5x5.5)
包裝: 托盤
其它名稱: 74LVCH322244AEC/G
74LVCH322244AEC/G-ND
935281138557
September 1993
10
Philips Semiconductors
Product specication
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Note to the 74HCT AC Characteristics
1. tPZH only applicable in the divide-by-1 mode and X1 must be HIGH.
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITION
25
40 to 85
40 to 125
VCC
(V)
VI
OTHER
MIN
TYP
MAX
MIN
MAX
MIN
MAX
tPHL/tPLH
propagation
delay X1 to
OUT
divide-by-1
24
40
50
60
ns
4.5
Fig.7
S1 = GND
S2 = GND
tPHL/tPLH
propagation
delay X1 to
OUT
divide-by-2
29
50
62
75
ns
4.5
Fig.7
S1 = GND
S2 = VCC
tPHL/tPLH
propagation
delay X1 to
OUT
divide-by-4
35
60
75
90
ns
4.5
Fig.7
S1 = VCC
S2 = GND
tPHL/tPLH
propagation
delay X1 to
OUT
divide-by-8
40
70
87
105
ns
4.5
Fig.7
S1 = VCC
S2 = VCC
tPLZ/tPHZ
3-state output
disable time
MR to OUT
21
35
43
52
ns
4.5
Fig.8
tPZ
3-state output
enable time
MR to OUT
16
30
37
45
ns
4.5
Fig.8
tPZH
3-state output
enable time
MR to OUT
22
38
47
57
ns
4.5
Fig.8
see note 1
tTHL/tTLH
output
transition time
512
15
19
ns
4.5
Fig.7
tW
clock pulse
width X1,
HIGH or LOW
10
6
12
15
ns
4.5
Fig.7
tW
master reset
pulse width
MR; LOW
16
8
20
24
ns
4.5
Fig.9
trem
removal time
MR to X1
24
12
30
36
ns
4.5
Fig.9
fmax
maximum clock
pulse frequency
50
85
40
33
MHz
4.5
Fig.7
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