參數(shù)資料
型號: 74LVCH322244AEC,51
廠商: NXP Semiconductors
文件頁數(shù): 12/14頁
文件大?。?/td> 0K
描述: IC BUFF DVR TRI-ST 32BIT 96LFBGA
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 3,500
系列: 74LVCH
邏輯類型: 緩沖器/線路驅(qū)動器,非反相
元件數(shù): 8
每個(gè)元件的位元數(shù): 4
輸出電流高,低: 12mA,12mA
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 96-LFBGA
供應(yīng)商設(shè)備封裝: 96-LFBGA(13.5x5.5)
包裝: 帶卷 (TR)
其它名稱: 74LVCH322244AEC-T
74LVCH322244AEC-T-ND
935263930518
September 1993
7
Philips Semiconductors
Product specication
Programmable ripple counter with
oscillator; 3-state
74HC/HCT6323A
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Note to the 74HC AC Characteristics
1. tPZH only applicable in the divide-by-1 mode and X1 must be HIGH.
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITION
25
40 to 85
40 to 125
VCC
(V)
VI
OTHER
MIN
TYP
MAX
MIN
MAX
MIN
MAX
tPHL/tPLH
propagation
delay X1 to
OUT divide by 1
61
22
19
185
37
31
230
46
39
275
55
47
ns
2.0
4.5
6.0
Fig.7
S1 = GND
S2 = GND
tPHL/tPLH
propagation
delay X1 to
OUT divide by 2
74
27
23
235
47
40
290
58
49
350
70
60
ns
2.0
4.5
6.0
Fig.7
S1 = GND
S2 = VCC
tPHL/tPLH
propagation
delay X1 to
OUT divide by 4
91
33
28
285
57
48
355
71
60
425
85
72
ns
2.0
4.5
6.0
Fig.7
S1 = VCC
S2 = GND
tPHL/tPLH
propagation
delay X1 to
OUT divide by 8
105
38
32
335
67
57
415
83
71
500
100
85
ns
2.0
4.5
6.0
Fig.7
S1 = VCC
S2 = VCC
tPLZ/tPHZ
3-state output
disable time
MR to OUT
75
15
13
150
30
26
185
37
31
225
45
38
ns
2.0
4.5
6.0
Fig.8
tPZL
3-state output
enable time
MR to OUT
36
13
11
150
30
26
185
37
31
225
45
38
ns
2.0
4.5
6.0
Fig.8
tPZH
3-state output
enable time
MR to OUT
61
22
19
200
40
34
250
50
43
300
60
51
ns
2.0
4.5
6.0
Fig.8
note 1
tTHL/tTLH
output
transition time
14
5
4
60
12
10
75
15
13
90
19
15
ns
2.0
4.5
6.0
Fig.7
tW
clock pulse
width X1,
HIGH or LOW
50
10
9
17
6.0
5
60
12
10
75
15
13
ns
2.0
4.5
6.0
Fig.7
tW
master reset
pulse width
MR; LOW
80
16
14
22
8
7
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.9
trem
removal time
MR to X1
100
20
17
19
7
6.0
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.9
fmax
maximum clock
pulse frequency
10
50
59
17
85
100
8
40
47
6.6
33
39
MHz
2.0
4.5
6.0
Fig.7
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