參數(shù)資料
型號(hào): 74LVCH322244A
廠(chǎng)商: NXP Semiconductors N.V.
英文描述: 32-bit buffer/line driver;with 30Ω series termination resistors; with 5-volt tolerant inputs/outputs (3-State)(帶30Ω系列終端電阻器,5V輸入/輸出容限的32位緩沖器/線(xiàn)驅(qū)動(dòng)器(三態(tài)))
中文描述: 32位緩沖器/線(xiàn)路驅(qū)動(dòng)器,與30Ω串聯(lián)終端電阻,與5伏容限輸入/輸出(3國(guó))(帶30Ω系列終端電阻器,5V的輸入/輸出容限的32位緩沖器/線(xiàn)驅(qū)動(dòng)器(三態(tài)))
文件頁(yè)數(shù): 2/16頁(yè)
文件大小: 77K
代理商: 74LVCH322244A
1999 Aug 31
2
Philips Semiconductors
Product specification
32-bit buffer/line driver; with 30
series termination
resistors; 5 V input/output tolerant; 3-state
74LVC322244A;
74LVCH322244A
FEATURES
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range of 1.2 to 3.6 V
CMOS low power consumption
MULTIBYTE
flow-trough standard pin-out architecture
Low inductance multiple power and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
Bus hold on data inputs (74LVCH322244A only)
Integrated 30
termination resistors
Typical output ground bounce voltage:
V
OLP
<0.8 V at V
CC
= 3.3 V; T
amb
= 25
°
C
Typical output V
OH
undershoot voltage:
V
OHV
>2 V at V
CC
= 3.3 V; T
amb
= 25
°
C
Power-off disabled outputs, permitting live insertion
Plastic fine-pitch ball grid array package.
DESCRIPTION
The74LVC(H)322244Aisahigh-performance,low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of
these devices in a mixed 3.3 and 5 V environment.
The74LVC(H)322244Aisa32-bitnon-invertingbuffer/line
driver with 3-state outputs. The 3-state outputs are
controlled by the output enable inputs 1OE and 2OE.
A HIGH on input nOE causes the outputs to assume a
high-impedance OFF-state.
The 74LVC(H)322244A is designed with 30
series
termination resistors in both HIGH and LOW output stages
to reduce line noise.
To ensure the high-impedance state during power-up or
power-down, input nOE should be tied to V
CC
through a
pull-up resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
The 74LVCH322244A bus hold data input circuit
eliminates the need for external pull-up resistors to hold
unused or floating data inputs at a valid logic level (see
Fig.3).
QUICK REFERENCE DATA
Ground = 0 V; T
amb
= 25
°
C; t
r
= t
f
2.5 ns.
Note
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
C
I
C
PD
propagation delay nA
n
to nY
n
input capacitance
power dissipation capacitance per
buffer
C
L
= 50 pF; V
CC
= 3.3 V
2.9
5.0
25
ns
pF
pF
V
I
= GND to V
CC
; note 1
相關(guān)PDF資料
PDF描述
74LVC322244A 32-bit buffer/line driver; with 30 ohm series termination resistors; 5 V input/output tolerant; 3-state
74LVC322244AEC Hex Buffers And Line Drivers With 3-State Outputs 16-TSSOP -40 to 85
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