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參數(shù)資料
| 型號： | 74LVC74APWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual D-type flip-flop with set and reset; positive-edge trigger |
| 中文描述： | LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 99K |
| 代理商： | 74LVC74APWDH |
Philips Semiconductors
Product Specification
74LVC74A
Dual D-type flip-flop with set and reset;
positive-edge trigger
2
1998 Jun 17
853-2070 19589
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
In accordance with JEDEC standard no. 8-1A.
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Output drive capability 50 transmission lines @ 85
°
C
DESCRIPTION
The 74LVC74A is a high-performance, low-voltage Si-gate CMOS
device and superior to most advanced CMOS compatible TTL
families.
The 74LVC74A is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (S
D
) and (R
D
)
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D inputs must be stable one set-up time prior to the
LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action in all data inputs makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL/
t
PLH
Propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
C
L
= 50 pF;
V
CC
= 3.3 V
3.6
3.5
3.5
ns
f
max
C
I
C
PD
Maximum clock frequency
250
MHz
Input capacitance
5.0
pF
Power dissipation capacitance per flip-flop
Notes 1 and 2
30
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
(C
L
×
V
CC2
×
f
o
) + (V
O2
/R
L
)
×
duty factor LOW, where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
ORDERING INFORMATION
PACKAGES
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
74LVC74A D
74LVC74A DB
74LVC74A PW
NORTH AMERICA
74LVC74A D
74LVC74A DB
74LVC74APW DH
DWG NUMBER
SOT108-1
SOT337-1
SOT402-1
PIN CONFIGURATION
SV00491
1R
D
1D
1CP
1S
D
1Q
1Q
GND
V
CC
2R
D
2D
2CP
2S
D
2Q
2Q
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LOGIC SYMBOL (IEEE/IEC)
SV00332
4
3
2
1
10
11
12
13
5
6
9
8
S
C1
1D
R
S
C2
2D
R
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