參數(shù)資料
型號: 74LVC74ADB,118
廠商: NXP Semiconductors
文件頁數(shù): 14/19頁
文件大?。?/td> 0K
描述: IC DUAL D FF POS-EDGE 14SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,000
系列: 74LVC
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類型: D 型
輸出類型: 差分
元件數(shù): 2
每個元件的位元數(shù): 1
頻率 - 時鐘: 250MHz
延遲時間 - 傳輸: 2.5ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 24mA,24mA
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-SSOP(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
74LVC74A
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 20 November 2012
4 of 19
NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
5.2 Pin description
6.
Functional description
[1]
H = HIGH voltage level
L = LOW voltage level
X = don’t care
[1]
H = HIGH voltage level
L = LOW voltage level
= LOW-to-HIGH transition
Qn+1 = state after the next LOW-to-HIGH CP transition
X = don’t care
Table 2.
Pin description
Symbol
Pin
Description
1RD
1
asynchronous reset-direct input (active LOW)
1D
2
data input
1CP
3
clock input (LOW-to-HIGH, edge-triggered)
1SD
4
asynchronous set-direct input (active LOW)
1Q
5
true output
1Q
6
complement output
GND
7
ground (0 V)
2Q
8
complement output
2Q
9
true output
2SD
10
asynchronous set-direct input (active LOW)
2CP
11
clock input (LOW-to-HIGH, edge-triggered)
2D
12
data input
2RD
13
asynchronous reset-direct input (active LOW)
VCC
14
supply voltage
Table 3.
Function table[1]
Input
Output
nSD
nRD
nCP
nD
nQ
L
H
XXH
L
H
L
XXL
H
L
XXH
H
Table 4.
Function table[1]
Input
Output
nSD
nRD
nCP
nD
nQn+1
HH
LLH
HH
HHL
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