參數(shù)資料
型號: 74LVC3GU04
廠商: NXP Semiconductors N.V.
英文描述: TRIPLE INVERTER
中文描述: 3個(gè)反相器
文件頁數(shù): 2/14頁
文件大?。?/td> 79K
代理商: 74LVC3GU04
9397 750 14545
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 31 January 2005
2 of 14
Philips Semiconductors
74LVC3G34
Triple buffer gate
3.
Quick reference data
[1]
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
The condition is V
I
= GND to V
CC
.
[2]
4.
Ordering information
5.
Marking
Table 1:
GND = 0 V; T
amb
= 25
°
C.
Symbol
Parameter
t
PHL
, t
PLH
propagation
delayinput nAto
output nY
Quick reference data
Conditions
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
V
CC
= 5.0 V; C
L
= 50 pF; R
L
= 500
Min
-
-
-
-
-
-
Typ
3.8
2.4
2.5
2.2
1.9
2.5
Max Unit
-
-
-
-
-
-
ns
ns
ns
ns
ns
pF
C
I
input
capacitance
power
dissipation
capacitance per
gate
C
PD
V
CC
= 3.3 V
[1] [2]
-
14
-
pF
Table 2:
Type number
Ordering information
Package
Temperature range Name
74LVC3G34DP
40
°
C to +125
°
C
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 1
×
1.95
×
0.5 mm
Version
SOT505-2
TSSOP8
74LVC3G34DC
40
°
C to +125
°
C
VSSOP8
SOT765-1
74LVC3G34GT
40
°
C to +125
°
C
XSON8
SOT833-1
Table 3:
Type number
74LVC3G34DP
74LVC3G34DC
74LVC3G34GT
Marking codes
Marking code
V34
Y34
Y34
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