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參數(shù)資料
| 型號： | 74LVC273 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 85 |
| 中文描述： | 八路D型觸發(fā)器的復(fù)位觸發(fā)器，積極邊緣觸發(fā) |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 95K |
| 代理商： | 74LVC273 |
Philips Semiconductors
Product specification
74LVC273
Octal D-type flip-flop with reset; positive-edge trigger
2
1998 May 20
853-2064 19419
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Conforms to JEDEC standard 8-1A
Inputs accept voltages up to 5.5V
CMOS low power consumption
Direct interface with TTL levels
Output drive capability 50
transmission lines @ 85
°
C
DESCRIPTION
The 74LVC273 is a low-voltage Si-gate CMOS device, superior to
most advanced CMOS compatible TTL families.
The 74LVC273 has eight edge-triggered , D-type flip-flops with
individual D inputs and Q outputs. The common clock (CP) and
master reset (MR) inputs load and reset (clear) all flip-flops
simultaneously. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW independently of clock or data inputs
by a LOW voltage level on the MR input.
The device is useful for applications where the true output only is
required and the clock and master reset are common to all storage
elements.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
=t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CP to Qn;
MR to Q
n
C
L
= 50pF
V
CC
= 3.3V
6.0
6.0
ns
f
max
C
I
Maximum clock frequency
230
MHz
Input capacitance
5.0
pF
C
PD
Power dissipation
capacitance per flip-flop
V
I
= GND to V
CC1
22
pF
NOTE:
1
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
x f
i
(C
L
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
V
CC2
f
o
) where:
ORDERING INFORMATION
PACKAGES
20-Pin Plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
74LVC273 D
74LVC273 DB
74LVC273 PW
NORTH AMERICA
74LVC273 D
74LVC273 DB
74LVC273PW DH
DWG NUMBER
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
V
CC
15
16
17
18
19
20
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
SY00051
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
MR
Master reset input (active LOW)
2, 5, 6,
9, 12, 15,
16, 19
Q0 – Q7
Flip-flop outputs
3, 4, 7,
8, 13, 14,
17, 18
D0 – D7
Data inputs
10
GND
Ground (0V)
11
CP
Clock input (LOW-to-HIGH,
edge-triggered)
20
V
CC
Positive power supply
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| 74LVC273PWDH | Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 85 |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 74LVC2734AE4Q | 制造商:Integrated Device Technology Inc 功能描述: |
| 74LVC273AE4Q | 制造商:Integrated Device Technology Inc 功能描述: |
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| 74LVC273APGG8 | 制造商:Integrated Device Technology Inc 功能描述:Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin TSSOP T/R 制造商:Integrated Device Technology Inc 功能描述:IC FLIP FLOP OCTAL D 20-TSSOP |
| 74LVC273AQ20-13 | 功能描述:IC D-TYPE POS TRG SNGL 20QFN 制造商:diodes incorporated 系列:74LVC 包裝:剪切帶（CT） 零件狀態(tài):有效 功能:復(fù)位 類型:D 型 輸出類型:非反相 元件數(shù):1 每元件位數(shù):8 頻率 - 時鐘:230MHz 不同 V，最大 CL 時的最大傳播延遲:7.3ns @ 3.3V，50pF 觸發(fā)器類型:正邊沿 電流 - 輸出高，低:24mA，24mA 電壓 - 電源:1.65 V ~ 3.6 V 電流 - 靜態(tài):10μA 輸入電容:4pF 工作溫度:-40°C ~ 125°C（TA） 安裝類型:表面貼裝 封裝/外殼:20-VFQFN 裸露焊盤 標(biāo)準(zhǔn)包裝:1 |
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