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參數(shù)資料
| 型號： | 74LVC1G04 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-TSSOP -40 to 85 |
| 中文描述： | 具有3態(tài)輸出的四路2至1線路數(shù)據(jù)選擇器/多路復(fù)用器 16-TSSOP封裝；-40℃到85℃ |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 91K |
| 代理商： | 74LVC1G04 |
1.
General description
The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior
to most advanced CMOS compatible TTL families.
The input can be driven from either 3.3 Vor 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging backflow current through the device when
it is powered down.
The 74LVC1G175 is a single positive edge triggered D-type flip-flop with individual
data (D) input, clock (CP) input, master reset (MR) input, and Q output.
The master reset (MR) is an asynchronous active LOW input and operate independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall times.
2.
Features
I
Wide supply voltage range from 1.65 V to 5.5 V
I
5 V tolerant inputs for interfacing with 5 V logic
I
High noise immunity
I
Complies with JEDEC standard:
N
JESD8-7 (1.65 V to 1.95 V)
N
JESD8-5 (2.3 V to 2.7 V)
N
JESD8B/JESD36 (2.7 V to 3.6 V).
I
±
24 mA output drive (V
CC
= 3.0 V)
I
ESD protection:
N
HBM EIA/JESD22-A114-B exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V.
I
CMOS low power consumption
I
Latch-up performance exceeds 250 mA
I
Direct interface with TTL levels
I
Inputs accept voltages up to 5 V
I
Multiple package options
I
Specified from
40
°
C to +85
°
C and
40
°
C to +125
°
C.
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 01 — 18 October 2004
Product data sheet
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LVC1G02 | Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-TSSOP -40 to 85 |
| 74LVC1GU04 | Inverter |
| 74LVC1G86 | 2-input EXCLUSIVE-OR gate |
| 74LVC1G18 | 1-of-2 non-inverting demultiplexer with 3-state deselected output |
| 74LVC1G00 | Single 2-input NAND gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVC1G04_09 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single inverter |
| 74LVC1G04_1010 | 制造商:DIODES 制造商全稱:Diodes Incorporated 功能描述:SINGLE INVERTER GATE |
| 74LVC1G04DBVR | 制造商:Texas Instruments 功能描述:Logic Circuit, Inverter, LCX/LVC-CMOS, 5 Pin, Plastic, TSOP |
| 74LVC1G04DCKT | 制造商: 功能描述: 制造商:Texas Instruments 功能描述: 制造商:undefined 功能描述: |
| 74LVC1G04FS3-7 | 功能描述:Inverter IC 1 Channel 4-X2DFN (0.80x0.80) 制造商:diodes incorporated 系列:74LVC 包裝:剪切帶（CT） 零件狀態(tài):有效 邏輯類型:反相器 電路數(shù):1 輸入數(shù):1 特性:- 電壓 - 電源:1.65 V ~ 5.5 V 電流 - 靜態(tài)（最大值）:200μA 電流 - 輸出高，低:32mA，32mA 邏輯電平 - 低:0.7 V ~ 0.8 V 邏輯電平 - 高:1.7 V ~ 2 V 不同 V，最大 CL 時的最大傳播延遲:3.7ns @ 5V，50pF 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 供應(yīng)商器件封裝:4-X2DFN（0.80x0.80） 封裝/外殼:4-XFDFN 裸露焊盤 標(biāo)準(zhǔn)包裝:1 |
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