參數(shù)資料
型號(hào): 74LVC1G00GM,115
廠商: NXP Semiconductors
文件頁數(shù): 1/19頁
文件大?。?/td> 0K
描述: IC SNGL 2-IN NAND GATE 6-XSON
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 5,000
系列: 74LVC
邏輯類型: 與非門
電路數(shù): 1
輸入數(shù): 2
電源電壓: 1.65 V ~ 5.5 V
電流 - 靜態(tài)(最大值): 200µA
輸出電流高,低: 32mA,32mA
邏輯電平 - 低: 0.7 V ~ 0.8 V
邏輯電平 - 高: 1.7 V ~ 2 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 1.8ns @ 5V,50pF
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 6-XSON,SOT886(1.45x1)
封裝/外殼: 6-XFDFN
包裝: 帶卷 (TR)
1.
General description
The 74LVC1G00 provides the single 2-input NAND function.
Input can be driven from either 3.3 V or 5 V devices. These features allow the use of
these devices in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2.
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
24 mA output drive (V
CC =3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 Cto+85 C and 40 C to +125 C
74LVC1G00
Single 2-input NAND gate
Rev. 10 — 2 July 2012
Product data sheet
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