參數(shù)資料
型號(hào): 74LVC169D,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 6/24頁(yè)
文件大?。?/td> 0K
描述: IC SYNC 4BIT BIN COUNTER 16SOIC
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 50
系列: 74LVC
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向: 上,下
元件數(shù): 1
每個(gè)元件的位元數(shù): 4
計(jì)時(shí): 同步
計(jì)數(shù)速率: 150MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SO
包裝: 管件
其它名稱: 74LVC169D
74LVC169D-ND
935210570112
74LVC169
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 29 November 2012
14 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 11. Set-up and hold times for the input (Dn) and parallel enable input (PE)
001aaa654
GND
th
tsu
th
tsu
VM
VI
CP input
PE input
Dn input
VI
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 12. Set-up and hold times for count enable inputs (CEP and CET) and control input (U/D)
001aaa655
th
tsu
th
tsu
GND
VI
VM
GND
VI
CP input
CEP, CET, U/D input
Table 8.
Measurement points
Supply voltage
Input
Output
VCC
VI
VM
1.2 V
VCC
0.5
V
CC
0.5
V
CC
1.65 V to 1.95 V
VCC
0.5
V
CC
0.5
V
CC
2.3 V to 2.7 V
VCC
0.5
V
CC
0.5
V
CC
2.7 V
1.5 V
3.0 V to 3.6 V
2.7 V
1.5 V
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