參數(shù)資料
型號(hào): 74LVC163D,112
廠商: NXP Semiconductors
文件頁數(shù): 2/20頁
文件大小: 0K
描述: IC SYNC 4BIT BIN COUNTER 16SOIC
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 50
系列: 74LVC
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 4
復(fù)位: 同步
計(jì)時(shí): 同步
計(jì)數(shù)速率: 150MHz
觸發(fā)器類型: 正邊沿
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SO
包裝: 管件
其它名稱: 74LVC163D
74LVC163D-ND
935210540112
74LVC163
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 20 November 2012
10 of 20
NXP Semiconductors
74LVC163
Presettable synchronous 4-bit binary counter; synchronous reset
11. AC waveforms
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9.
Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and the maximum frequency
mgu762
CP input
Qn, TC output
tPHL
tPLH
tW
VM
VOH
VI
GND
VOL
VM
1/fmax
VM
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. Input (CET) to output (TC) propagation delays
mgu763
CET input
TC output
tPLH
tPHL
GND
VI
VM
VOH
VOL
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 11. Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master
reset to clock (CP) removal times
mgu764
th
tsu
th
tsu
VM
VI
GND
VI
GND
CP input
MR input
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