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參數(shù)資料
| 型號： | 74LVC161284TTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER |
| 中文描述： | 低壓高速IEEE1284收發(fā)器 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 217K |
| 代理商： | 74LVC161284TTR |
1/11
May 2003
I
HIGH SPEED: t
PD
= 9ns (MAX.) at V
CC
= 3V
LOW POWER DISSIPATION:
I
CC
=20
μ
A (MAX) at V
CC
=3.6V T
A
=85°C
TTL COMPATIBLE INPUTS
V
IH
=2V (MIN) V
IL
=0.8(MAX)
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 3.0V to 3.6V
A PORT HAVE STANDARD 4mA TOTEM
POLE OUTPUT
I
I
I
I
I
B PORT HIGH DRIVE SOURCE/SINK
CAPABILITY OF 14mA
I
SUPPORT IEEE STD 1284-I (LEVEL 1 TYPE)
AND IEEE STD 1284-II (LEVEL 2 TYPE) FOR
BIDIRECTIONAL PARALLEL
COMMUNICATIONS BETWEEN PERSONAL
COMPUTER ANT PRINTING PERIPHERALS
I
TRANSLATION CAPABILITY ALLOW
OUTPUTS ON CABLE SIDE TO INTERFACE
WITH 5V SIGNAL
I
PULL-UP RESISTOR INTEGRATED ON ALL
OPEN-DRAIN OUTPUT ELIMINATE THE
NEED FOR DISCRETE RESISTOR
I
REPLACE THE FUNCTION OF TWO
74LVC1284 DEVICES
DESCRIPTION
The 74LVC161284 contains eight high speed non
inverting bidirectional buffers and eleven control/
status non-inverting buffers with open drain
outputs
fabricated
in
technology. It’s intended to provide a standard
signaling
method
for
peripheral in an Extended Capabilities Port Mode
(ECP). The HD (Active HIGH) input pin enables
the Cable port to switch from Open Drain to a high
drive totem pole output, capable of sourcing 14mA
on all thirteen buffer and 84mA on PERI LOGIC
OUTPUT buffer. The DIR input determines the
direction of data flow on the bidirectional buffers.
DIR (Active HIGH) enables data flow from A port
to B port. DIR (Active LOW) enables data flow
from B port to A port. It is available in the
commercial temperature range.
silicon
gate
C
2
MOS
a
bi-direction
parallel
74LVC161284
LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER
ORDER CODES
PACKAGE
TUBE
T & R
TSSOP
74LVC161284TTR
TSSOP
PIN CONNECTION
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