參數(shù)資料
型號: 74LVC109
廠商: NXP Semiconductors N.V.
英文描述: Dual JK flip-flop with set and reset; positive-edge trigger
中文描述: 雙JK觸發(fā)器設(shè)置和復(fù)位觸發(fā)器,積極邊緣觸發(fā)
文件頁數(shù): 5/10頁
文件大?。?/td> 103K
代理商: 74LVC109
Philips Semiconductors
Product specification
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
1998 Apr 28
5
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
°
C to +85
°
C
TYP
1
UNIT
MIN
MAX
V
IH
HIGH level Input voltage
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= –100
μ
A
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –12mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –24mA
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100
μ
A
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
V
CC
2.0
V
V
IL
LOW level Input voltage
GND
V
0.8
V
CC
V
CC
V
CC
V
CC
0.5
V
OH
HIGH level output voltage
0.2
V
CC
V
0.6
1.0
0.40
V
OL
LOW level output voltage
GND
0.20
V
0.55
I
I
Input leakage current
V
CC
= 3 6V; V = 5 5V or GND
I
= 5.5V or GND
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
0 1
0.1
5
μ
A
I
CC
Quiescent supply current
0.1
10
μ
A
I
CC
Additional quiescent supply current per
input pin
V
CC
= 2.7V to 3.6V; V
I
= V
CC
–0.6V; I
O
= 0
5
500
μ
A
NOTE:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
°
C.
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
2.5 ns; C
L
= 50 pF; R
L
= 500 ; T
amb
= –40 C to +85 C
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V
±
0.3V
V
CC
= 2.7V
TYP
NO TAG
UNIT
MIN
TYP
1
MAX
MIN
MAX
t
PHL
/t
PLH
Propagation delay
nCP to nQ, nQ
Propagation delay
nS
D
to nQ
nR
D
to nQ
Propagation delay
nS
D
to nQ
nR
D
to nQ
Clock pulse width
HIGH or LOW
Set or reset pulse width
HIGH or LOW
Removal time
nS
D,
nR
D
to nCP
Set-up time
nJ, nK to CP
Hold time
nJ, nK to nCP
Maximum clock pulse
frequency
Figures 1, 3
4.3
7.5
8.5
ns
t
PLH
Figures 2, 3
4.5
8.0
9.0
ns
t
PHL
Figures 2, 3
5.2
9.0
10
ns
t
W
Figure 1
3.3
2.0
ns
t
W
Figure 2
3.0
ns
t
rem
Figure 2
3.0
ns
t
su
Figure 1
2.5
ns
t
h
Figure 1
2.0
ns
f
max
Figure 1
150
225
MHz
NOTE:
1. These typical values are at V
CC
= 3.3V and T
amb
= 25
°
C.
相關(guān)PDF資料
PDF描述
74LVC109PWDH Dual JK flip-flop with set and reset; positive-edge trigger
74LVC10A Octal Bus Transceivers With 3-State Outputs 20-TSSOP -40 to 85
74LVC10APWDH Triple 3-input NAND gate
74LVC10 Triple 3-input NAND gate
74LVC10DB Triple 3-input NAND gate
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74LVC109ASO 制造商:Integrated Device Technology Inc 功能描述:74LVC109ASO - Bulk
74LVC109AXTDC 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述:
74LVC109AXTPY 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述:
74LVC109D 制造商:NXP Semiconductors 功能描述:Flip Flop JK# -Type Pos-Edge 2-Element 16-Pin SO
74LVC109D,112 功能描述:觸發(fā)器 3.3V DUAL JK SET RESET POS RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel